BS IEC 60748-23-2-2002 Semiconductor devices - Integrated circuits - Hybrid integrated circuits and film structures - Manufacturing line certification - Internal visual inspection .pdf

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1、BRITISH STANDARD BS IEC 60748-23-2: 2002 Semiconductor devices Integrated circuits Part 23-2: Hybrid integrated circuits and film structures Manufacturing line certification Internal visual inspection and special tests ICS 31.200 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW

2、BS IEC 60748-23-2:2002 This British Standard, having been prepared under the direction of the Electrotechnical Sector Policy and Strategy Committee, was published under the authority of the Standards Policy and Strategy Committee on 21 June 2002 BSI 21 June 2002 ISBN 0 580 39866 8 National foreword

3、This British Standard reproduces verbatim IEC 60748-23-2:2002 and implements it as the UK national standard. The UK participation in its preparation was entrusted by Technical Committee EPL/47, Semiconductors, to Subcommittee EPL/47/1, Film and hybrid integrated circuits, which has the responsibilit

4、y to: A list of organizations represented on this subcommittee can be obtained on request to its secretary. From 1 January 1997, all IEC publications have the number 60000 added to the old number. For instance, IEC 27 has been renumbered as IEC 60027-1. For a period of time during the change over fr

5、om one numbering system to the other, publications may contain identifiers from both systems. Cross-references The British Standards which implement international publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards

6、 Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard do

7、es not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European deve

8、lopments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the IEC title page, pages 2 to 97 and a back cover The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication

9、 Amd. No. Date CommentsINTERNATIONAL STANDARD IEC 60748-23-2 QC 165000-2 First edition 2002-05 Semiconductor devices Integrated circuits Part 23-2: Hybrid integrated circuits and film structures Manufacturing line certification Internal visual inspection and special tests Dispositifs semiconducteurs

10、 Circuits intgrs Partie 23-2: Circuits intgrs hybrides et structures par films Certification de la ligne de fabrication Contrle visuel interne et essais spciaux Reference number IEC 60748-23-2:2002(E) 2 607-8423-2 CEI:0220(E) CONTENTS FOREWORD.7 INTRODUCTION.9 1 Scope.10 2 Normative references .10 3

11、 Definitions 11 4 Apparatus.18 5 Procedure.18 5.1 General .18 5.2 Sequence of inspection .19 5.3 Inspection control19 5.4 Re-inspection19 5.5 Exclusions.19 5.6 Magnification.19 5.7 Format and conventions 19 5.8 Interpretations.20 6 Thin film element inspection .20 6.1 Operating metallization non-con

12、formances “high magnification“ .20 6.2 Passivation non-conformances “high magnification“ 26 6.3 Glassivation non-conformances, “high magnification“ 27 6.4 Substrate non-conformances “high magnification“ .28 6.5 Foreign material non-conformances “low magnification“ 30 6.6 Thin film resistor non-confo

13、rmances, “high magnification“ .31 6.7 Laser trimmed thin film resistor non-conformances, “high magnification“ .36 6.8 Multilevel thin film non-conformances, “high magnification“ .45 6.9 Coupling (air) bridge non-conformances “high magnification“ 45 7 Planar thick film element inspection47 7.1 Operat

14、ing metallization non-conformances “low magnification“47 7.2 Substrate non-conformances, “low magnification“51 7.3 Thick film resistor non-conformances, “low magnification“ .54 7.4 Trimmed thick film resistor non-conformances, “low magnification“56 7.5 Multilevel thick film non-conformances, “low ma

15、gnification“.58 7.6 All thin film capacitors and overlay capacitors used in GaAs microwave devices, “low magnification“ 59 8 Active and passive elements 59 9 Element attachment (assembly), “magnification 10 to 60 “ .59 9.1 Solder connections (general appearance)59 9.2 Element attachment requirements

16、 .60 9.3 Leaded and leadless element attachment64 9.4 Dual-in-line integrated circuit attachment (butt joints) 64 9.5 Axial and radial leaded components (lap joints).67 9.6 Components with feet (combined butt and lap joints).68 9.7 Leadless chip carriers .70 10 Element orientation 71 11 Separation71

17、 BSIEC60748232:2002 BSI21June2002 2 BSIEC60748233:2001 BSI21June2002 2 BSIEC60748232:2002 BSI21June2002 2067-8423-2 CEI:0220(E) 3 12 Bond inspection, magnification 30 to 60 72 12.1 Ball bonds .72 12.2 Wire wedge bonds.72 12.3 Tailless bonds (crescent).73 12.4 Compound bond73 12.5 Beam lead.74 12.6 M

18、esh bonding76 12.7 Ribbon bonds 76 12.8 General .77 13 Internal leads (e.g. wires, ribbons, beams, wire loops, ribbon loops, beams, etc.), “magnification 10 to 60 “77 14 Screw tabs and through-hole mounting, magnification 3 to 10 .78 15 Connector and feedthrough centre contact soldering, magnificati

19、on 10 to 30 78 16 Package conditions, solder assemblies, lead frame attachments, conformal coating, “magnification 10 to 60 “.81 16.1 Package conditions .81 16.2 Lead frame attachment81 16.3 Conformal coating .84 17 Non-planar element inspection .84 17.1 General non-planar element non-conformances,

20、“low magnification“ .84 17.2 Foreign material non-conformances “low magnification“ 85 17.3 Ceramic chip capacitor non-conformances “low magnification“85 17.4 Tantalum chip capacitor non-conformances, “low magnification“ .88 17.5 Parallel plate chip capacitor non-conformances, “low magnification“ .88

21、 17.6 Inductor and transformer non-conformances, “low magnification“ 89 17.7 Chip resistor non-conformances, “low magnification“.90 18 Surface acoustic wave (SAW) element inspection.92 18.1 Operating metallization non-conformances “low magnification“92 18.2 Substrate material non-conformances “low m

22、agnification“ .92 18.3 Foreign material non-conformances “low magnification“ 92 19 Summary93 20 Radiographic inspection .93 20.1 Requirements93 21 Particle impact noise detection (PIND) test .95 21.1 General .95 21.2 Equipment.95 21.3 Test procedure96 21.4 Failure criteria.96 21.5 Lot acceptance96 2

23、1.6 The detail specification97 Figure 1 Class H Metallization scratch criteria.14 Figure 2 Class H Metallization scratch criterion.21 Figure 3 Class H Metallization width reduction at bonding pad criterion 21 Figure 4 Class K Metallization width pad reduction at bonding pad criterion21 Figure 5 Clas

24、s H Metallization void criterion22 Figure 6 Class H Interdigitated capacitor metallization void criterion.23 BSIEC60748232:2002 BSI21June2002 3 BSIEC60748233:2001 BSI21June2002 3 BSIEC60748232:2002 BSI21June2002 3 4 607-8423-2 CEI:0220(E) Figure 7 Class K Interdigitated capacitor metallization void

25、criterion .23 Figure 8 Class H Operating metallization protrusion criterion 24 Figure 9 Class H Interdigitated capacitor metallization protrusion criterion24 Figure 10 Class H Metallization alignment criterion.25 Figure 11 Class K Metallization alignment criterion .25 Figure 12 Class H Wrap-around c

26、onnection unmetallized area criterion 26 Figure 13 Class H Passivation non-conformance criteria.26 Figure 14 Class H Laser trimmed glassivation non-conformance criteria .27 Figure 15 Class H Separation and chipout criteria.29 Figure 16 Class H Crack criteria .29 Figure 17 Class K Semicircular crack

27、criterion 30 Figure 18 Class H Film resistor width reduction at terminal by voids criterion31 Figure 19 Class H Film resistor width reduction at terminal by necking criterion32 Figure 20 Class H Resistor width reduction by voids and scratches criteria.32 Figure 21 Class H Metal/resistor overlap crit

28、erion .33 Figure 22 Class H Contact overlap criterion 33 Figure 23 Class H Resistor separation criteria 34 Figure 24 Class H Substrate irregularity criterion 34 Figure 25 Class H Resistor width increase criterion 35 Figure 26 Class H Protrusion of resistor material criterion.35 Figure 27 Class H Bri

29、dging of resistor material criteria36 Figure 28 Class H Kerf width criteria.37 Figure 29 Class H Detritus criterion for self-passivating resistor materials 37 Figure 30 Class H Resistor loop element detritus criterion for self-passivating resistor materials.38 Figure 31 Bridging of detritus between

30、rungs in the active area of a resistor ladder structure criterion38 Figure 32 Class H Resistor ladder structure nicking and scorching criteria exceptions.39 Figure 33 Class H Resistor loop nicking and scorching criteria exceptions40 Figure 34 Class H Laser nicking criteria exception for the last run

31、g of a resistor ladder40 Figure 35 Class H Resistor ladder sidebar trim criterion41 Figure 36 Class H Laser trim misalignment criteria41 Figure 37 Class H Laser trim kerf extension into metallization criteria.42 Figure 38 Class H Resistor width reduction at metallization interface criteria 42 Figure

32、 39 Class H Resistor width reduction by trimming criteria 43 Figure 40 Class H Resistor width reduction and untrimmed resistor material criteria .44 Figure 41 Class H Laser trim pitting criterion.44 Figure 42 Class H Insulating material extension criteria 45 Figure 43 Class H and Class K Coupling (a

33、ir) bridge criteria.46 Figure 44 Class H Metallization scratch criteria.47 Figure 45 Class H Metallization width reduction at bonding pad criteria 48 Figure 46 Class K Metallization width reduction at bonding pad criteria48 BSIEC60748232:2002 BSI21June2002 4 BSIEC60748233:2001 BSI21June2002 4 BSIEC6

34、0748232:2002 BSI21June2002 4067-8423-2 CEI:0220(E) 5 Figure 47 Class H Metallization void criteria48 Figure 48 Class H Metallization protrusion criterion.50 Figure 49 Class H Metallization overlap criterion.50 Figure 50 Class H Wrap-around connection unmetallized area criterion 51 Figure 51 Class H

35、Separation and chipout criteria.52 Figure 52 Class H Additional crack criteria52 Figure 53 Class K Semicircular crack criterion 53 Figure 54 Class H Resistor width reduction at terminal caused by voids criterion54 Figure 55 Class H Resistor width reduction at terminal by neck-down criterion54 Figure

36、 56 Class H Resistor width reduction criteria .55 Figure 57 Class H Resistor overlap criterion .55 Figure 58 Class K Resistor overlap criterion55 Figure 59 Resistor overlap criterion .56 Figure 60 Class H Kerf width criteria.57 Figure 61 Class H Laser trim kerf extension into metallization criteria.

37、57 Figure 62 Class H Resistor width reduction and untrimmed resistor material criteria .58 Figure 63 Class H Dielectric extension criteria 59 Figure 64 Solder wetting criteria 60 Figure 65 Solder wetting contact angle 60 Figure 66 Element attachments61 Figure 67 Balling of die attach material 62 Fig

38、ure 68 Adhesive irregularities and cracks63 Figure 69 Adhesive string criterion.63 Figure 70 Package post criteria64 Figure 71 Dual-in-line package leads solder wetting.65 Figure 72 Lead to pad registration .66 Figure 73 Lap joint solder wetting 67 Figure 74 Combined butt and lap joints solder wetti

39、ng Reject68 Figure 75 Combined butt and lap joints solder wetting Accept.69 Figure 76 Solder fillet coverage criteria69 Figure 77 Acceptable symmetrical element orientation.71 Figure 78 Bond dimensions72 Figure 79 Bond dimensions73 Figure 80 One bond used to secure two common wires73 Figure 81 a) Be

40、am lead area and location74 Figure 81 b) Beam lead area and location75 Figure 82 Acceptable/rejectable tears or voids in ribbon weld area 75 Figure 83 Criterion for strands along the mesh.76 Figure 84 Criterion for continuous conducting paths.76 Figure 85 Centre contact orientations to substrate .79

41、 Figure 86 Centre contact overlap to substrate79 Figure 87 a) Void criterion80 Figure 87 b) Crack/adhesion criteria 80 BSIEC60748232:2002 BSI21June2002 5 BSIEC60748233:2001 BSI21June2002 5 BSIEC60748232:2002 BSI21June2002 5 6 607-8423-2 CEI:0220(E) Figure 87 c) Excess solder criterion .80 Figure 87

42、d) Insufficient solder criterion .80 Figure 87 e) Solder criteria 80 Figure 88 Lead frame registration 81 Figure 89 Dual-in-line lead frame registration.82 Figure 90 Solder bridging.82 Figure 91 Lead frame solder fillets.83 Figure 92 Single finger solder fillet.83 Figure 93 Substrate to lead frame f

43、ork gap 84 Figure 94 Class H Metallization protrusion criterion.84 Figure 95 Class H Metal plate exposure criteria 86 Figure 96 Class H Crack criteria .86 Figure 97 Class H Delamination criteria 86 Figure 98 Class H Termination non-conformance criteria 87 Figure 99 Class H Metallized edge non-confor

44、mance criteria 87 Figure 100 Class H Metallization extension criterion .88 Figure 101 Class H Crack in dielectric criterion.89 Figure 102 Class H Resistor width reduction criterion .90 Figure 103 Class H Termination width criterion .90 Figure 104 Class H Substrate non-conformance criteria91 Figure 1

45、05 Class H Termination material build-up criteria .91 Figure 106 Class H Termination material splatter criteria 92 Table 1 Shaker frequencies .97 BSIEC60748232:2002 BSI21June2002 6 BSIEC60748233:2001 BSI21June2002 6 BSIEC60748232:2002 BSI21June2002 6067-8423-2 CEI:0220(E) 7 INTERNATIONAL ELECTROTECH

46、NICAL COMMISSION _ SEMICONDUCTOR DEVICES INTEGRATED CIRCUITS Part 23-2: Hybrid integrated circuits and film structures Manufacturing line certification Internal visual inspection and special tests FOREWORD 1) The IEC (International Electrotechnical Commission) is a worldwide organization for standar

47、dization comprising all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also part