ARMY MIL-C-14882 A-1981 CIRCUIT CARD ASSEMBLY 10559295 REPLY GATING《10559295 回击控制 电路卡装配》.pdf

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1、MIL-C- 14882A(AR) 30 June 1981 SUPERSEDING .- MIL-C- 14882(AR) 2 MARCH 1970 MILITARY SPECIFICATION CIRCUIT CARD ASSEMBLY: 10559295 REPLY GATING This specification is approved for use by the US Army Armament Research and Development Command (ARRADGOMI and is available for use by all Departments and A

2、gencies of the Deparment of Defense. 1. SCOPE 1.1 Scope. This specification establishes the requirements and quality assurance provisions for the Circuit Card Assembly: which is the A4 component of the Electronics Unit, 11743131. 10559295 Reply Gating 2. APPLICABLE DOCUbENTS 2.1 Issues of documents.

3、 The following documents of the issue in effect on date of invitation for bids or request for proposal, form a part of this specification to the extent specified herein. SPEC1 FI CATION MILITARY MIL -F- 13 926 MIL-1-45607 MIL-STD-45662 STANDARDS MILITARY MIL-STD- 105 MIL-STD-8 10 PiCe Control Materi

4、al; General Specification Governing the Manufacture and Inspection of Inspection Equipment, Supply and Maintenance of Ca li brat i on S y s tem Requi rement s Sampling Procedures and Tables for Inspection by At tributes Environmental Test Methods FSC: . THIS DOCUMENT CONTAINS 23 PAGES. 1240 Provided

5、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-/ MIL -C- 14 8 8 2A ( AR DRAWINGS ARRAEOM 10559295 Circuit Card Assembly - Reply Gating Inspection Equipment 11750202 11750432 11 82 1458 11 82 1520 11 821 647 Packaging Data Sheet P 105 5 9 2 95 Automatic Card

6、 and Unit - Test Set Adapter, Relay Gating Shock Adapter, Plate Vib Horz-Vert Plane/ Automatic Test Assembly Central Processor Vibration/Shock Test Fixture Shock Z Unit Packaging of Circuit Card Assembly - Reply Gating 10559295 (Copies of specifications, standards, drawings, and publications require

7、d by contractors in connection with specific procurement functions should be obtained from the procuring activity or as directed by the contracting of fi Cer. 1 a- 2 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3. REQUIREMENTS 3.1 Fabrication. The

8、 reply gating circuit card assembly, herein referred to as the assembly, shall be manufactured in accordance with Drawing 10559295 and drawings pertaining thereto and, when assembled, shall meet the requirements of this specification. (See 4.5 .i) 3.1.1 Function. The assembly shall provide the follo

9、wing functions: Func ti oii a. b. d. e. f. h. i. j. k. C. g* Res et i he 1OKM gate Range inti1 bit- Range gate Counters reset Counters crystal oscillator frequency Clock pulse count Replies counter Test circui try-manual Malfunction 7 Te st oscilla tor 3.1.2 General specifications. The following pro

10、visions of MIL-F-13926 apply: (See 4.5.1) a. Order of precedence b. Dimensions and tolerances c. Inorganic protective surf ace finishes d. Part identification and marking e . Workmans hip 3.1.3 Ambient conditions. Standard ambient conditions shall be as f o 11 ows : a. Temperature 73O + 18OF b. Rela

11、tive humidity 50 percent + 30 percent. C. Atmospheric pressure 28.5 + 2.0 -3.0 ia. Hg. 3.2 First article. When specified (see 6.21, the contractor shall furnish sample units for first article inspection and approval (see 4.4 and 6.2). 3.3 Performance. Unless otherwise specified, the assembly shall m

12、eet the performance requirements specified herein under standard ambient conditions of 3.1.3. 3.3.1 Loads, power and signals. Switch, S1, shall be depressed during requirements 3.3.1.1 through 3 . 3.1.8. 3 r Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

13、S-,-,-MIL-C- 14882A( AR) I TABLE I. Loads, power and signals. litem I Condition Loads loo 1.2 NAND Gage 1.3 NAND Gate 1.4 NAND Gage 1.5 NAND Gate 1.6 1 NAND Gate NAND Gate 1.7 1.8 Res is tor 1.9 Res is tor 2.0 Power sources I 2.1 5 Vdc 2.2 15Ydc 3.0 1 Signal source Connect i on s I Characteristics 4

14、 gates - DT micro 1 946 3 gates - DT micro 1 946 3 gates - DT micro 1 946 3 gates - DT micro 1 946 5 gates - DT micro 1 946 3 gates - DT micro 1 946 3 gates - DT micro 1 946 1500 ohms +5% 1500 ohms +5% - - Tolerance Maximum ripple (volts) (mV p-p) + .2 25 - +. 7 25 - Logical one: 4 - +1 volts Logica

15、l zero: .2 + .2 volt Pulse width and pzise repetition rate variable and as specified herein Connect between the following pins of P1: 1A and 36B 26B and 36B 25A and 36B 24B and 36B 2B and 36B 3A and 36 B 4B and 36B 12B and 15A 6B and 15A Applied be tween the following pins of P1: 15A(+)and 16B(-) 15

16、B(+)and 36B(-) Applied as speci- fied herein P- I 4 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C- 14882A(AR) - 0.1 MILLISECOND (ms) 25 ms (AT 50% VOLTAGE POINTS) 3.3.1.1 -Turn-on reset the. With the application of the 5-Vdc supply voltage of

17、 table I, the waveform and time interval of the output at P1-29A shall be as shown in figure 1. (See 4.6.2.1) TYPE-A SIGNAL- PI- 29A 4.2 IV OUTPUT 1 - 0.2 50.2v - 4 1 20.2 MICRO- 3.3.1.2 10-KM gate. on figure 2, and applied to P1-lOB, the output at P1-12B shall be as shown on figure 2. (See 4.6.2.2)

18、 With the type -A signal of table I adjusted as shown 5 I 50.2 ms (50% VOLTAGE) POINTS - 4.2 2 1 V c- 82515 PI- 126 OUTPUT - msec 0.2 i 0.2 v OUTPUT t,1400 NANOSECONDS (ns) (10 TO 90% OF VOLTAGE) INPUT AND OUTPUT 4 Il00 ns (90 TO 10% OF VOLTAGE) FIGURE 2. IO-KM gate waveform. Provided by IHSNot for

19、ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL -C- 1488 2A ( AR) 3.3.1.3 Minimum range inhibit. With the digital input signal of table I applied to the input pins as specified in table II, but with the signal to P1-29A momentarily a logical zero for each item except i

20、tem 5, the digital output signal shall appear at the output pin as specified in table II for each condition. (See 4.6.2.3) I tem TABLE II. Minimum range inhibit. Input Pins of 13A 32B 34 10B 1 O 1 1 1 O 1 O 1 O 1 1 1 O 1 O 1 O 1 O 1 O 1 O 9A 1 1 O O O O 2 9A P1 Output 6B I 1 H 1 H 1 H 1 L 1 H O “ -

21、i/ Legend: 1 = logical one, type-A O = logical zero, type-A H = 4.2 +lV L = 0.2 +0.2v - 3.3.1.4 Maximum range gate. With the digital type-A signals of table I (See 4.6.2.4) applied in the following sequence for each item of table III: a. Logical zero to P1-32B. h. c. Momentarily logical zero to P1-1

22、3A and then P1-29A. d. Waveforms of figure 3 to the specified pins. Digital signals to the group of input pins specified in table III. The voltages at the output pins shall be asspecified in table III for each input condition, 6 Provided by IHSNot for ResaleNo reproduction or networking permitted wi

23、thout license from IHS-,-,-MIL-C- 14 8 8 2A(AR TYPE-A SIGNAL - - - LOGICAL ZERO FIGURE 3. TYPE-A signal inputs to PI-9A and PI-IOB- -4 t 1 msec maximum rame aate. TYPE-A SIGNAL - 3.3.1.5 Counters 1, 2, and 3 reset. With the digital type-A signal of table I applied as specified in table IV, and the w

24、aveforms of figure 4 applied last, followed by a momentary logical zero type-A signal applied again to P1-29A, the voltage at P1-24B, P1-25A and P1-26B shall be .2 - +.2 Vdc. (See 4.6.2.5) f- 2 f 0.4 msec - - - -LOGICAL ZERO TABU3 IV. Counters reset. P1 Input 29A 3 1A 27A 3 2B 9A 10B Type-A signal M

25、omentarily logical zero Logical one Logical zero Logical. zero Waveform of figure 4 Waveform of figure 4 7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-PI-9A INPUT TYPE-A SIGNAL -1 Il ONE - - LOGICAL ZERO PI-1OB INPUT II 1 ONE TYPE-A SIGNAL U- - -

26、 - -LOGICALZERO _)_ - 2 i 0.2 msec z. t and tf 100 ns both waveforms r FIGURE 4. TYPE-A sicinal ineuts to PI-9A and Pl-106-counters. _ _- MIL-C-LLI882A LE 777770b 027777 5 a ,. MIL-C-l4882A( AR) 3.3.1.6 Counters 1, 2 and 3 crystal oscillator frequency. With the digital signals of table I applied as

27、specified in table IV, and waveform of figure 4 applied last, the waveform shown on figure 5 shall appear at P1-24B, P1-25A9 and P1-26B st a frequency of 14.990 + .O02 MHz or 14.9855 +0.002 MH,. (See 4.6.2.6) - - 3.521 V 0.2 i 0.2 v FIGURE 5. Counter 1,2,3 waveform. 3.3.1.6.1 Inhibit signal. With th

28、e operating conditions of 3.3.1.6 in effect, applying the waveform shown on figure 6 as specified shall inhibit the square wave outputs at P1-24B, P1-25A9 and P1-26B within 75 ns. The steady state output voltages shall be either 3.5 - +1 Vdc or .2 - +.2 Vdc. LOGICAL ONE PI- 31A INPUT TYPE- A SIGNAL

29、-1 I LOGICALZERO . 4 210 ns FIGURE 6. Inhibit signal. 8 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-24B 25A 26B P1 Input -LI-I .- 2 9A 3 1A 27A 32B 10B 9A MIL -C- 14 8 8 2A ( AR) TYPE-A Signal Momentarily logical zero Logical one Logical zero Log

30、ical zero Waveform of figure 7 Waveform of figure 7 3.3.1.7 Clock pulse count. With the digital signals of table I applied as specified in table V, and the waveforms of figure 7 applied last, the number of pulses appearing at P1-24B, P1-25A9 and P1-26B shall be as specified in table VI. (See 4.6.2.7

31、) I -6.66 f .O2 msec -1 -9.99 +, 0.2 msec- 4 13 f 1 msec - TABLE V. Clock waveform. TABLE VI. Clock pulse count. I Number of pulses I P1 output I I 50 + 1 150 + 1 100 z 1 - I 1 ,-u-u-u-u-r o tfO ns t,L100 ns (both waveforms) 1 = Logical one O = Logical zero FIGURE 7. “A8 trigger and video waveforms.

32、 9 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C- 14882A( AR) 3.3.1.8 Replies counter. With the digital signals of table I applied as specified in table VII, followed by the application of the input signals shown on figure 8 to the specified

33、pins, the output wave forms shown on figure 8 shall appear at the specified pins. The signals may be recurring. 4.6.2.8) (See TABLE VII. Replies counter. P1 Input I- TYPE-A signal I 32B Logical zero 3 1A Logical one 27A Logical zero 13A Ihment aril y logical zero PI-29A Input Logical one type-A Logi

34、cal zero + 1 20.1 msec -1 1- 3i1 msec Logical one Logical zero PI-1OB Input type-A + 2 20.2 msec Logical one PI-9A Input type-A (10 or more puises) - Logical zero -p + 2 i 0.2 msec Pulse width = 1 .O 2 0.1 msec I e 4 0.4 msec OUTPUT VOLTAGES - -*i PI-IA Output If-. 4 tO.4 msec I I l I -I 1 O 1 1- 4

35、iO.4 msec I PI-2B Output -t 8 20.9 msec PI-3A Output I - O PI-4B Output tr and tf4 100 ns 1 = 3.5 +,IV o = 0.2 2 0.2v FIGURE 8. Output waveforms. 10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL -C- 1488 2A(AR) P1-32B Input 3.3.1.9 Test circuit

36、ry. (See 4.6.2.9) 3.3.1.9.1 Manual. With the following sequential input conditions: Waveforms Application 1st 2 nd 3rd 4th a. Logical one type-A signal applied to P1-31A, logical zero type-A signal applied to P1-27A and P1-34B. output P1-1A P1-2B P1-3A 3.5 +1 v 0.2 *.2 v 0.2 +.2 v 0.2 T.2 v 3.5 +i v

37、 0.2 5.2 v 3.5 *i v 3.5 Ti v 0.2 T.2 v 0.2 T.2 - v 0.2 7.2 - v 3.5 71 - v b, Switch SI depressed. C. Logical wt-o tvpe-A signal applied momentarily to P1-13A and with repeated application four times, of the signals of figure 9 to the specified pins. The voltages at the output pins shall be as specif

38、ied in table VIII. P1-9A Input type-A signal Logical one Logical zero 7 52 msec i 7 t2 msec i- 7 +-2 mec Pulse width = 1 t 0.2 nisec FIGURE 9. Test signals, TABLE VIII. Output voltages. 11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I_-_- MIL-C-1

39、4882A li! M 7777706 0277751 7 MIL -C- 14 8 8 2A ( AR ) 3.3.1.9.2 Malfunction 7. With the digital signals of table I applied as specified in table IX, switch S1 depressed, and with the waveforms of figure 9 applied as specified, the output voltage at P1-5A shall be as shown on figure 10. TABLE IX. Ma

40、lfunction signals. P1 Input TYPE-A Signal I I I 31A 34B 2 7A 13A Logical one Logical zero Logical zero Momentarily logical zero I I - 4.2 2 IV PI-5A Output 1 5 0.2 ms _I 0.2 t 0.2v FIGURE 10. Output waveforms. 3.3.1.9.2.1 Output voltage. With the logical zero type-A signal of table I applied momenta

41、rily to P1-29A and with a logical zero type-A signal applied to P1-13A, the output at .P1-5A shall be 4.2 - cl Vdc. 3.3.1.9.3 Test oscillator. With the logical zero type-A signal of table I applied to P1-32B and P1-34B, the outputs at the indicated pins shall be as specified on figure 11. PI-IA Outp

42、ut -,- 80 ? 50 msec - 3.5 4 IV I 0.2 +, 02v 1.8 ? 1.0 ms- I 4.2 ?IV 0.2 f 0.2v 80 f 50 msec c Pl-7A and =r PI-29A Output 6 FIGURE 11. Oscillator waveforms. 12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C- 14 88 2A( AR) 3.4 finvironmental. 3.

43、4.1 Shock, The assembly shall be capable of operating as specified herein after exposure under the conditions of 3.1.3 to three half sine wave shock pulses of 40 2 4 gravity unit (g) for a duration of 18 + 3 milliseconds (msec) applied in each direction along three mutually perpendycular axes. In ad

44、dition, the assembly shall be capable of withstanding three half sine wave shock pulses of 100.0 + 10.0 g for a duration of 1.5 2 0.2 msec applied in each direction along three mutually perpendicular axes. (See 4.6.3.1) 3.4.2 Vibration. The assembly shall be capable of operating as specified herein

45、after exposure under the conditions of 3.1.3 to the vibration profile of figure 12. Duration of exposure shall be not less than 80 minutes in each of three mutually perpendicular axes. (See 4.6.3.2) b 3.4.3 Operating temperature. The assembly shall be capable of operating as specified herein over th

46、e operating temperature range of -25OF to +125OF. (See 4.6.3.3, 4.63.4 and 4.6.3.5) 3.4.4 Storage temperature. The assembly shall be capable of operating as specified herein after exposure to storage temperatures ranging from -65OF to 160OF. (See 4.6.3.3, 4.6.3.4 and 4.6.3.5). 13 Provided by IHSNot

47、for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C- 14882A (AR) 14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- 4. QUALITY ASSURANCE PROVISIONS 4.1 Responsibility for inspection. Unless otherwise specified in the

48、 contract, the contractor is responsible for the performance of all inspection requirements as specified herein. Except as otherwise specified in the contract, the contractor may use his own or any other facilities suitable for the performance of the inspection requirements specified herein, unless disapproved by the Government. The Government reserves the right to perform any of the inspections set forth in the specification where such inspections are deemed necessary to assure supplies and services conform to prescribed requirements. 4.2 C