ANSI VITA 1-1994 VME64《VME64》.pdf

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1、ANSI/VITA 1-194 (R202) American National Standard for VME64 Secretariat VMEbus International Trade Asociation Approved 1994, Reaffirmed 2002 American National Standards Institute, Inc. This standard is being maintained under the stabilized maintenance option of the American National Standards Instit

2、ute. Requests for the withdrawal of or revisions to this standard should be directed to the technical director of VITA at stating the rationale for the request. The requestor will receive a written response within 60 days. VMEbus International Trade Asociation PO Box 19658, Fountain Hills, AZ 85269

3、 PH: 480-837-7486, FAX: Contact VITA Office E-mail: , URL: http:/ (This page left blank intentionally.)ANSI/VITA 1-1994 (R2002)American National Standardfor VME64SecretariatVMEbus International Trade AssociationApproved 1994, Reaffirmed 2002American National Standards Institute, Inc.AbstractThe VME6

4、4 specification establishes a framework for 8-, 16-, 32, and 64-bit parallel-buscomputer architectures that can implement single and multiprocessor systems. It is based onthe VMEbus specification released by the VMEbus Manufacturers Group (now VITA) in Augustof 1982. This bus includes the initial fo

5、ur basic subbuses: (1) data transfer bus, (2) priorityinterrupt bus, (3) arbitration bus, and (4) utility bus. Other architectures with other subbusesare possible within this VME framework.The data transfer bus will support 8-, 16-, 32-, and 64-bit data transfers in multiplexed andnon multiplexed fo

6、rm. The transfer protocols are asynchronous with varying degrees ofhandshaking dependent on the speeds required. The priority interrupt subsystem providesreal-time interrupt services to the system. The allocation of bus mastership is performed bythe arbitration subsystem which allows the implementat

7、ion of several prioritizationalgorithms. The utility bus provides the system with power plus power-up and power-downsynchronization. The mechanical specifications of boards, backplanes, subracks, andenclosures are based on IEC 297 and IEEE 1101.1 specifications, also known as the Eurocardform factor

8、. Additional standards exist that can be used as sub-busses to this architecture fordata transfers transactions, peripheral interfaces and intra-crate communications amongcompatible modules.AmericanNationalStandardApproval of an American National Standard requires verificationby ANSI that the requir

9、ements for due process, consensus, andother criteria for approval have been met by the standardsdeveloper.Consensus is established when, in the judgment of the ANSIBoard of Standards Review, substantial agreement has beenreached by directly and materially affected interests.Substantial agreement mea

10、ns much more than a simplemajority, but not necessarily unanimity. Consensus requiresthat all views and objections be considered, and that aconcerted effort be made toward their resolution.The use of American National Standards is completelyvoluntary; their existence does not in any respect preclude

11、anyone, whether he has approved the standards or not, frommanufacturing, marketing, purchasing, or using products,processes, or procedures not conforming to the standards.The American National Standards Institute does not developstandards and will in no circumstances give an interpretation ofany Ame

12、rican National Standard. Moreover, no person shallhave the right or authority to issue an interpretation of anAmerican National Standard in the name of the AmericanNational Standard Institute. Requests for interpretationsshould be addressed to the secretariat or sponsor whose nameappears on the titl

13、e page of this standard.CAUTION NOTICE: This American National Standard may berevised or withdrawn at any time. The procedures of theAmerican National Standards Institute require that action betaken periodically to reaffirm, revise, or withdraw this standard.Purchases of American National Standards

14、may receive currentinformation on all standard by calling or writing the AmericanNational Standards Institute.Published byVMEbus International Trade AssociationPO Box 19658, Fountain Hills, AZ 85269Certain portions of this document are derived from portions of IEEE Std 1014-1987 IEEE Standard for aV

15、ersatile Backplane Bus: VMEbus, Copyright 1987 by the Institute of Electrical and ElectronicsEngineers, Inc. and are adapted and reprinted with the permission of the IEEE. The IEEE disclaims anyresponsibility or liability resulting from the placement and use in this publication.Copyright 2003 by VME

16、bus International Trade AssociationAll rights reserved.NOTE: The users attention is called to the possibility that compliance with this standard mayrequire use of one or more inventions covered by patent rights.By publication of this standard, no position is taken with respect to the validity of suc

17、h claimsor of any patent rights in connection therewith. The patent holders have, however, filed astatement of willingness to grant a license under these rights on reasonable and non-discriminatory terms and conditions to applicants desiring to obtain such a license for use ofthis standard. Details

18、may be obtained from the publisher.No part of this publication may be reproduced in any form, in an electronic retrieval system orotherwise, without prior written permission of the publisher.Printed in the United States of America - R1.15ISBN 1-885731-02-7ANSI/VITA 1-1994 (R2002) iiTable of Contents

19、Abstract xForeword .xiVMEbus Specification Geneology.xiiiChapter 1 1Introduction to the VMEbus Specification .11.1 VMEbus Specification Objectives.11.2 VMEbus Interface System Elements 11.2.1 Basic Definitions11.2.1.1 Terms Used to Describe the VMEbus Mechanical Structure11.2.1.2 Terms Used to Descr

20、ibe the VMEbus Functional Structure.21.2.1.3 Types of Cycles on the VMEbus .51.2.2 Basic VMEbus Structure61.3 VMEbus Specification Diagrams.71.4 Specification Terminology91.4.1 Signal Line States .101.4.2 Use of the Asterisk (*) 101.4.3 Keyword Numbering111.5 Protocol Specification.111.5.1 Interlock

21、ed Bus Signals.111.5.2 Broadcast Bus Signal.121.6 System Examples and Explanations12Chapter 2 13Data Transfer Bus .132.1 Introduction.132.1.1 Enhancements132.2 Data-Transfer-Bus Lines.142.2.1 Addressing Lines.162.2.2 Address Modifier Lines .202.2.3 Data Lines.232.2.4 Data Transfer Bus Control Lines.

22、262.2.4.1 AS*262.2.4.2 DS0* and DS1*.262.2.4.3 DTACK* 262.2.4.3.1 Rescinding DTACK*. .272.2.4.4 BERR* .272.2.4.5 WRITE* .272.2.4.6 RETRY*.272.3 DTB Modules - Basic Description282.3.1 Master .282.3.2 Slave322.3.3 Bus Timer342.3.4 Location Monitor 36Table of ContentsANSI/VITA 1-1994 (R2002) iii2.3.5 A

23、ddressing Phases and Modes.372.3.6 Basic Data Transfer Capabilities392.3.7 Block Transfer Capabilities 422.3.8 Read-Modify-Write Capability.452.3.9 Unaligned Transfer Capability472.3.10 Address-Only Capability.502.3.11 Lock Capability512.3.12 Configuration ROM / Control And Status Register Capabilit

24、y.522.3.13 Retry Capability572.3.14 Interaction Between DTB Functional Modules 582.4 Typical Operation602.4.1 Typical Data-Transfer Cycles .602.4.2 Address Pipelining 672.5 Data-Transfer-Bus Acquisition.682.6 DTB Timing Rules and Observations .70Chapter 3 121Data Transfer Bus Arbitration 1213.1 Bus

25、Arbitration Philosophy 1213.1.1 Types Of Arbitration1213.2 Arbitration Bus Lines .1233.2.1 Bus Request And Bus Grant Lines.1253.2.2 Bus Busy Line (BBSY*) 1253.2.3 Bus Clear Line (BCLR*)1253.3 Functional Modules1263.3.1 Arbiter 1263.3.3 Data Transfer Bus Master.1333.3.3.1 Release Of The DTB.1333.3.3.

26、2 Acquisition Of The DTB.1343.3.3.3 Other Information 1343.4 Typical Operation.1353.4.1 Arbitration Of Two Different Levels Of Bus Request.1353.4.2 Arbitration Of Two Bus Requests On The Same Bus Request Line 1393.5 Race Conditions Between Master Requests and Arbiter Grants .144Chapter 4 145Priority

27、 Interrupt Bus.1454.1 Introduction1454.1.1 Single Handler Systems 1454.1.2 Distributed Systems 1454.2 Priority Interrupt Bus Lines1484.2.1 Interrupt Request Lines1494.2.2 Interrupt Acknowledge Line1494.2.3 Interrupt Acknowledge Daisy-Chain - IACKIN*/IACKOUT*1494.3 Priority Interrupt Bus Modules - Ba

28、sic Description1504.3.1 Interrupt Handler .1514.3.2 Interrupter .1534.3.3 IACK Daisy-Chain Driver .157Table of ContentsANSI/VITA 1-1994 (R2002) iv4.3.4 Interrupt Request Handling Capabilities1584.3.5 Interrupt Request Generation Capabilities1584.3.6 Status/Id Transfer Capabilities 1594.3.7 Interrupt

29、 Request Release Capabilities.1604.3.8 Interaction Between Priority Interrupt Bus Modules.1624.4 Typical Operation.1654.4.1 Single Handler Interrupt Operation.1664.4.2 Distributed Interrupt Operation.1664.4.2.1 Distributed Interrupt Systems With Seven Interrupt Handlers.1664.4.2.2 Distributed Interr

30、upt Systems With Two To Six InterruptHandlers.1684.4.3 Example: Typical Single Handler Interrupt System Operation .1694.4.4 Example: Prioritization of Two Interrupts In A Distributed InterruptSystem1724.5 Race Conditions.1744.6 Priority Interrupt Bus Timing Rules and Observations175Chapter 5 199Util

31、ity Bus1995.1 Introduction.1995.2 Utility Bus Signal Lines. 1995.3 Utility Bus Modules1995.3.1 System Clock Driver.1995.3.2 The Serial Bus Lines1995.3.3 Power Monitor2015.4 System Initialization and Diagnostics 2025.5 Power and Ground pins2075.6 Reserved Line .2075.7 Auto Slot Id.2085.8 Auto System

32、Controller.215Chapter 6 217Electrical Specifications.2176.1 Introduction2176.2 Power Distribution2176.2.1 DC Voltage Specifications .2186.2.2 Pin and Socket Connector Electrical Ratings.2196.3 Electrical Signal Characteristics.2196.4 Bus Driving and Receiving Requirements .2206.4.1 Bus Driver Defini

33、tions.2206.4.2 Driving And Loading RULEs For All VMEbus Lines.2216.4.2.1 Driving And Loading RULEs For High Current Three-State Lines2226.4.2.2 Driving And Loading RULEs For Standard Three-State Lines2226.4.2.3 Driving And Loading RULEs For High Current Totem-Pole Lines.2236.4.2.4 Driving And Loadin

34、g RULEs For Standard Totem-Pole Lines. 2246.4.2.5 Driving And Loading RULEs For Open-Collector Lines .2256.5 Backplane Signal Line Interconnections 2266.5.1 Termination Networks.226Table of ContentsANSI/VITA 1-1994 (R2002) v6.5.2 Characteristic Impedance2286.5.3 Additional Information 2296.6 User De

35、fined Signals 2306.7 Signal Line Drivers and Terminations.230Chapter 7 233Mechanical Specifications.2337.1 Introduction2337.2 VMEbus Boards.2347.2.1 Single Height Boards.2347.2.2 Double Height Boards .2357.2.3 Board Connectors2367.2.4 Board Assemblies.2377.2.5 Board Widths .2377.2.6 VMEbus Board War

36、page, Lead Length and Component Height2387.3 Front Panels2387.3.1 Handles2397.3.2 Front Panel Mounting 2407.3.3 Front Panel Dimensions2407.3.4 Filler Panels 2417.3.5 Board Ejectors/Injectors2427.4 Backplanes2427.4.1 Backplane Dimensional Requirements2437.4.2 Signal Line Termination Networks.2447.5 A

37、ssembly of VMEbus Subracks.2447.5.1 Subracks And Slot Widths 2447.5.2 Subrack Dimensions .2457.6 Conduction Cooled VMEbus Systems2457.7 VMEbus Backplane Connectors and VMEbus Board Connectors.2457.7.1 Pin Assignments For The J1/P1 Connector.2467.7.2 Pin Assignments For The J2/P2 Connector.247Appendi

38、x A 267Glossary of VMEbus Terms267Appendix B 275VMEBus Connector/Pin Description 275Appendix C 279Manufacturers Board Identification.279Appendix D 281Rule Index 281Table of ContentsANSI/VITA 1-1994 (R2002) viList of FiguresFigure 1 - 1 System Elements Defined By This Document3Figure 1 - 2 Functional

39、 Modules and Buses Defined by the Document.8Figure 1 - 3 Signal Timing Notation12Figure 2 - 1 Data Transfer Bus Functional Block Diagram15Figure 2 - 2 Block Diagram29Figure 2 - 3 Block Diagram32Figure 2 - 4 Block Diagram35Figure 2 - 5 Block Diagram36Figure 2 - 6 Four Ways That 32 Bits Of Data Might

40、Be Stored In Memory.47Figure 2 - 7 Four Ways That 16 Bits of Data Might Be Stored in Memory48Figure 2 - 34 Block Diagram53Figure 2 - 8 An Example of a Non-multiplexed Address, Single-Byte ReadCycle.61Figure 2 - 9 An Example Of A Multiplexed Address Double-Byte Write Cycle62Figure 2 - 10 An Example O

41、f A Non-multiplexed Address Quad-Byte WriteCycle.64Figure 2 - 35 An Example Of An Eight-Byte Block Read Cycle 65Figure 2 - 11 Data Transfer Bus Master Exchange Sequence 69Figure 2 - 12 Address Broadcast Timing - All Cycles.95Figure 2 - 13 A16, A24, A32 Master, Responding Slave, And Location Monitor9

42、6Figure 2 - 14 Master, Slave, and Location Monitor - A16, A24 and A32 AddressBroadcast Timing.97Figure 2 - 15 Master, Slave, And Location Monitor A16, A24, And A32 AddressBroadcast Timing.98Figure 2 - 27 Master, Slave And Location Monitor - A64 , A40, And ADOHAddress Broadcast Timing.99Figure 2 - 16

43、 Master, Slave, And Location Monitor Data Transfer Timing.100Figure 2 - 17 Master, Slave, And Location Monitor Data Transfer Timing.102Figure 2 - 28 Master, Slave And Location Monitor Data Transfer Timing104Figure 2 - 18 Master, Slave, And Location Monitor Data Transfer Timing.106Figure 2 - 19 Maste

44、r, Slave, And Location Monitor Data Transfer Timing.108Figure 2 - 29 Master, Slave And Location Monitor Data Transfer Timing110Figure 2 - 20 Master, Slave, And Location Monitor Data Transfer TimingSingle-Byte RMW Cycles112Figure 2 - 21 Master, Slave, and Location Monitor Data Transfer Timing .113Fig

45、ure 2 - 22 Address Strobe Inter-Cycle Timing .114Figure 2 - 23 Data Strobe Inter-Cycle Timing 114Figure 2 - 24 Data Strobe Inter-Cycle Timing 115Figure 2 - 25 Master, Slave, And Bus Timer Data Transfer Timing 115Figure 2 - 26 Master DTB Control Transfer Timing .116Figure 2 - 30 Master And Slave Data

46、 Transfer Timing 117Figure 2 - 31 Master And Slave Data Transfer Timing 118Figure 2 - 32 A40, MD32 Read-Modify-Write119Figure 2 - 33 Rescinding DTACK Timing 120Figure 3 - 1 Arbitration Functional Block Diagram122Figure 3 - 2 Illustration Of The Daisy Chain Bus Grant Lines124Figure 3 - 3 Block Diagra

47、m128Figure 3 - 4 Block Diagram132Figure 3 - 5 Arbitration Flow Diagram Two Requesters,136Figure 3 - 6 Arbitration Sequence Diagram Two Requesters, Two RequestLevels .138Figure 3 - 7 Arbitration Flow Diagram 140Figure 3 - 8 Arbitration Sequence Diagram .143Figure 4 - 1 Priority Interrupt Bus Function

48、al Diagram.146Figure 4 - 2 Interrupt Subsystem Structure.147Figure 4 - 3 Interrupt Subsystem Structure.148Table of ContentsANSI/VITA 1-1994 (R2002) viiFigure 4 - 4 IACKIN*/IACKOUT* DAISY-CHAIN 150Figure 4 - 5 Block Diagram152Figure 4 - 6 Block Diagram156Figure 4 - 7 Block Diagram157Figure 4 - 8 Rele

49、ase Of Interrupt Request Lines By ROAK And RORAInterrupters162Figure 4 - 9 An IACK Daisy-Chain Driver And Interrupter On The Same Board164Figure 4 - 10 Two Interrupters On The Same Board.165Figure 4 - 11 The Three Phases Of An Interrupt Sequence.166Figure 4 - 12 Two Interrupt Handlers, Each Monitoring One Interrupt .167Figure 4 - 13 Two Interrupt Handlers, Each Monitoring Several Interrupt 168Figure 4 - 14 Typical Single Handler Interrupt System Operation .170Figure 4 - 15 Typical Distributed Interrupt System With Two InterruptHandlers, Flow