ANSI EIA-469-D-2006 Test Method for Destructive Physical Analysis (DPA) of Ceramic Monololithic Capacitors《片状瓷电容器破坏性物理分析的试验方法》.pdf

《ANSI EIA-469-D-2006 Test Method for Destructive Physical Analysis (DPA) of Ceramic Monololithic Capacitors《片状瓷电容器破坏性物理分析的试验方法》.pdf》由会员分享，可在线阅读，更多相关《ANSI EIA-469-D-2006 Test Method for Destructive Physical Analysis (DPA) of Ceramic Monololithic Capacitors《片状瓷电容器破坏性物理分析的试验方法》.pdf（52页珍藏版）》请在麦多课文档分享上搜索。

1、ANSI/ElA-469-0-2006 Approved: April 6,2006 EIA STANDARD STANDARD TEST METHOD FOR DESTRUCTIVE PHYSICAL ANALYSIS (DPA) OF CERAMIC MONOLITHIC CAPACITORS EIA/E CA-469-D (Revision of EIA-469-C) APRIL 2006 Electronic Cornpanen it may include many finishing lots, depending on the control document. Interban

2、d dimension: The distance between opposite end metallization bands on a capacitor element. Interface: The junction of two layers in a layered device, for example, the junction of electrode to dielectric layers or between two ceramic sheet layers. Intermetallic: A solution of two metallic elements fo

3、rmed during reflow or due to certain other conditions involving temperature and time, for example, the copper/tin intermetallic formed between a copper surface and a tin/lead solder when the solder is reflowed against the copper surface. Knitline: Generally, the bonding interface between two layers

4、of bondable materials; these may be the same, similar, or different materials. Specifically, in ceramic multilayer capacitors, the interface of bonding between two ceramic sheets or a ceramic and metallic interface. Knitline delamination: Specifically, a delamination that occurs in one of the knitli

5、nes of an end margin, in the same plane as an opposed electrode. Leaching: The erosion of end metal from a chip capacitor due to the action of molten solder, wherein the end metal is dissolved and put into solution with the solder. Length: The dimension running from termination to termination. In so

6、me chip capacitor designs, the length may be less than the width of the element. Lot: The general designation of a quantity of product which is of the same raw material origin, design and lot date code, and was manufactured as a uniquely designated group through the same processes. This could be a c

7、hip lot, a finishing lot, or an inspection lot. Lot date code: A designation used for lot identification that is made up of following sequence: 1) a 2-digit year code; 2) a 2-digit week code; 3) an alpha or alphanumeric code that is unique for one lot manufactured during a given year and week, e.g.,

8、 9305ZX, 931 5A7, 91 51 L, etc. This identifier must be printed on each part or each package, and on all pertinent data, photographs, samples, etc. Margin: The ceramic portion of a chip element which envelopes the active area. Metallization band: The portion of the end metallization which extends al

9、ong the exterior of the chip from the end of the chip element toward its longitudinal center for distances varying generally from 0.25 mm to 1 .O2 mm (0.01 in to 0.04 in). Microcrack: A very fine narrow crack in the ceramic that is visible only at relatively high magnifications (generally above 150X

10、) with the aid of indirect or dark field or polarized lighting. True Microcrack occur due to internal chip element stresses or relief of such stresses. Mounting: The process, during DPA, consisting of setting the sample specimens up on an adhesive surface and surrounding them with a retainer ring, r

11、eady for pouring of the potting medium. Opposed electrodes: See 3.28, Electrically opposed electrodes. Overlap view: The longitudinal sectional view of monolithic capacitors, hybrids or leaded, showing the overlapped electrode edges, end margins, end metallizations, and chip to lead solder joint, th

12、e plane being perpendicular to the electrodes and ceramic layers (see figure C.1.). Copyright Electronic Components, Assemblies the maker of M-Pyrol is GAF If the product being decapsulated does not respond to the solvents recommended in this specification, the manufacturer of that product should be

13、 contacted for information on its decapsulation, regarding both chemical and procedure issues. When the above recommended decapsulants are used, the following is a correct procedure: 4.2.2.1 Decapsulation procedure a) Cut leads off to a length of approximately 1 .O mm (0.04 in). b) Place the devices

14、 to be decapsulated into a borosilicate glass (e.g., PyrexTM) beaker and cover them with approximately 13 mm (0.5 in) of the decapsulant (DMF or M-Pyrol). Cover the beaker with an appropriate watch glass. A refluxing flask system may be used to control and condense vapors. c) Set the beaker on a con

15、trolled heat source capable of 250 OC, cover and allow to reach the boiling point and adjust the heat to maintain a slow boiling action for a period of 30 min to 90 min, depending on the size and configuration of the encapsulated capacitor. DMF boils at slightly over 150 OC, while M-Pyrol boils at a

16、 little more than 200 OC. Smaller parts such as CKSI 1, CKS12, CKS05, and CKSO6 require less time in the boiling solvent (perhaps 30 min to 45 min), while larger parts such as CKS14 and CKS16 require progressively longer times (60 min to 90 min or even more). Scarifying the smooth surfaces of the en

17、capsulation or actually sanding away of some of the more massive parts of the encapsulation on larger devices may aid in the rapid penetration of the solvent. However, the risk of damaging the chip element or leads by such grinding always exists and great care must be exercised when using such techn

18、iques. Caution is the watchword for those performing chemomechanical decapsulation. d) At the end of the boiling period, turn the heat source off and allow the solvent to cool to less than 50 OC. Pour off the used solvent and dispose of it in an acceptable manner. e) Rinse the specimens thoroughly w

19、ith warm, running water for 2 min to 3 min, using approximately the middle one-third of the time to allow them to sit in water and diffuse out some of the trapped solvent. Then finish rinsing the parts with running water. f) Spread the parts on paper toweling or blotter paper. Using a short rigid ho

20、bby knife, “tease“ away the loosened and cracked encapsulation. If it does not chip away easily, more solvent treatment on the heat source is indicated. Never use excessive force in the removal of the treated encapsulation, since this will lead to damage to the capacitor and may lead to personal inj

21、ury to the operator. The additional boiling should be done in 15 min to 30 min increments on smaller parts and in longer increments on larger parts. g) After leaded capacitor elements have been removed from their encapsulations, they should be rinsed again in running water, then they should be dried

22、 and visually examined per 4.1 .I. After the visual inspection, clean the specimens per 4.2.3 and mount and cast them for sectioning per 4.2.4. SAFETY NOTE-Decapsulation chemicals must be used under an adequate fume hood to avoid breathing the vapors given off during heating. Also, some chemicals ma

23、y be absorbed through the skin or cause other injuries. See the manufacturers safety precautions. 4.2.3 Cleaning prior to mounting Copyright Electronic Components, Assemblies less time is required if finer grits are used. 2 Step 2 is not mandatory and may be omitted with good results. Manual polishi

24、ng after vibratory polishing is not recommended. After the vibratory polishing cycle, the sample rings must be removed from the specimen holders and cleaned in a mild detergent solution followed by a thorough water rinse, beginning with tap water and ideally followed by a rinse in deionized water. F

25、inally, isopropyl alcohol may be used immediately prior to viewing to remove any smear or foreign particle. For this purpose, a small dropper bottle is convenient and cotton swabs are ideal for cleaning and drying the surface to be viewed. If desired, the vibratory polishing may include a final 15-m

26、inute cycle using 0.05 pm gamma-alumina slurry, but this step is not mandatory. If performed, the final 15-minute cycle will require a separate polishing unit because of the much finer abrasive being used. NOTE-It is not practical to use the same polisher for both 0.3 pm and 0.05 pm polish. Also, sa

27、mple cleaning is required between the two sizes of abrasives. Other proven methods of automated polishing are acceptable if they produce comparable quality polished samples to the method recommended herein. 4.2.6.2 Manual polishing - alternate method Manual specimen polishing, where sample rings are

28、 hand held is rather operator dependent and surface relief is the rule rather than the exception. Sample specimens are more subject to damage such as pull- out and surface fracturing than with vibratory polishing. Nevertheless, a skilled operator can produce very high quality samples with manual tec

29、hniques. NOTE-Hand polishing should be kept to a minimum to avoid excessive surface relief and detail distortion (some of each is inevitable). Rough polishing shall consist of a 1 min to 2 min period on a short-napped cloth (Buehler Microcloth” or equivalent), using a polishing slurry of 1 .O pm or

30、0.3 vm alpha-alumina. Applied pressure should not exceed 14.0 kPa (2.0 psi), using less pressure during the last 30 seconds of this phase. The speed of the disc should range from 150 rpm to 250 rpm. By utilizing grits finer than 600 (e.g., 1200 or 2400) or comparable lapping film, one may eliminate

31、rough polishing and minimize fine polishing. Never polish any longer than necessary to produce a scratch-free surface for viewing. Fine polishing shall be accomplished using a slurry of 0.3 m or 0.05 m alumina in water. The fine polishing step will require from % to 1 minute using a wheel speed of 8

32、0 rpm to 125 rpm and slight hand pressure ranging from 3.5 kPa to 10.5 kPa (0.5 psi to 1.5 psi), the lesser pressure being applied during the last 30 seconds. The manual polishing steps are listed in table 5. Copyright Electronic Components, Assemblies or, they may be treated as dielectric voids, in

33、 which case the zone of interest must include all of the migratory segments (see figures D.l and D.2). 5.1.2 Dielectric voids and other voids in the ceramic a) Any void or aggregate of voids (cluster, series) between opposed electrodes which reduces the dielectric thickness by more than 50% of the a

34、verage dielectric thickness (see figures D.l and D.2). Copyright Electronic Components, Assemblies & Materials Association Provided by IHS under license with ECA Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-EIA-469-D Page 16 b) Any void or pinhole in a coverplat

35、e or in a side margin which reduces the coverplate thickness or the margin at that location to less than the minimum allowed by 5.1.3. NOTES 1) For industrial grade capacitors rated at less than 25 volts dc and/or where the designed dielectric is less than 0.02 mm (0.0008 in), consult the manufactur

36、er or an applications expert for appropriate minimum dielectric thickness requirements. 2) Where there is a question of true void dimensions, other analytical techniques may be employed to discriminate between defects and possible DPA processing artifacts and for assessing possible risk factors. 5.1

37、.3 Margin defects a) Side margins: Any side margin that displays a minimum margin less than the required minimum shown in table 6. Table Cide margins Rated voltage Minimum required side margin working volts dc mm (in) 25 0.025 (0.0010) 0.040 (0.0016) 0.050 (0.0020) 25 through 50 50 through 200 b) En

38、d margins: Any end margin with a minimum less than the values given in table 7. Table 7-End margins Rated voltage Minimum required end margin working volts dc mm (in) 25 0.040 (0.001 6) 0.050 (0.0020) 0.075 (0.0030) 25 through 50 50 through 200 c) Cover plate thickness: Any cover plate with a minimu

39、m thickness less than the values given in table 8. Table 8-Cover plate thickness Rated voltage Min. Required cover plate thickness working volts dc mm (in) 25 0.040 (0.001 6) 0.050 (0.0020) 0.075 (0.0030) 25 through 50 50 through 200 NOTE-Pertaining to all 5.1.3 margins, for working volts greater th

40、an 200 volts dc, consult an applications expert or the part suppliers for adequate margin requirements. 5.1.4 Cracks in the ceramic a) Any crack in the dielectric of the active area or any crack in the enveloping ceramic margins/borders that either reduces, or has the potential, through further prop

41、agation, to reduce the effective margins to a point less than the limits defined by 5.1.3. NOTE-Artifacts are excluded, since they are not defects. 5.1.5 Dielectric nonuniformities Copyright Electronic Components, Assemblies & Materials Association Provided by IHS under license with ECA Not for Resa

42、leNo reproduction or networking permitted without license from IHS-,-,-E IA-469-D Page 17 a) Any variation in dielectric thickness within the active area that results in more than 30% reduction in the thickness of an individual dielectric layer compared to the average nominal thickness of dielectric

43、 layers. NOTE-Design features for capacitance adjustment in low capacitance parts are exempt from this requirement. 5.1.6 Electrode nonuniformities a) Any variation in electrode thickness that causes an electrode to exceed two and one half times its average design thickness for more than 50% of the

44、total electrode length. b) Any abrupt increase in electrode thickness that reduces either adjacent dielectric thickness by more than 30% of the average nominal dielectric thickness. NOTE-For industrial grade capacitors less than 25 working volts dc and/or where the designed dielectric is less than 0

45、.02 mm (0.0008 in), consult the manufacture or applications expert for appropriate minimum dielectric thickness requirements. 5.1.7 End termination metallization defects of hybrid capacitors a) Any single void in the primary end termination metallization which spans more than 35% of the electrode st

46、ack thickness (see figure D.3). b) Any series of voids in the primary termination metallization exceeding 50% of the chip element thickness, T (see figure D.3). c) Clear evidence of loosening or lifting of end termination metallization from the terminating ceramic interface surface which spans more

47、than 10% of the terminating ceramic-end interface (see annex D). d) Clear evidence of loosening or lift up of a metallization side band (see annex D). NOTE-Lift up of plating overthrown beyond the primary end metallization bands is not a defect. 5.1.8 Barrier layer defects of hybrid capacitors a) An

48、y barrier layer, where required, which cannot be verified as present and uniformly deposited under light microscopy using dark field illumination (must appear as an interface between the primary end metallization and the solderable coat, as a minimum, to be acceptable). b) Any barrier layer, where r

49、equired, which displays intermittent or discontinuous coverage. NOTES 1 Barrier thickness measurements should be made at a minimum of 500X magnification. 2 Whenever serious doubt exists concerning the adequacy of a barrier layer following microscopic examination, then an independent sample (five or more pieces) may be submitted to a functional test for end metallization survivability in molten solder, agreed upon by the supplier and the purchaser. This test result may be used to augment the DPA findings or in lieu ofthose findings rega