SystemVerilog and UVM for the ABC system verification.ppt

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1、SystemVerilog and UVM for the ABC system verification,Francis Anghinolfi,14 Nov 2013,SystemVerilog MiniWorkshop,OUTLINE,The ABC verification environments SystemVerilog and UVM UVM techniques for the ABC system Development plans SystemVerilog for ABC system?,14 Nov 2013,SystemVerilog MiniWorkshop,2,T

2、he ABC verification environment,What is ABC function (in short),256 ch events,L0 trigger,R3 trigger,L1 trigger,Commands,Buffer,Actions,Buffer,Buffer,Readout,Packets,Verification does (in short) : Stimulation of hits, triggers, commands Analysis of packets (in relation to Stimulations),14 Nov 2013,Sy

3、stemVerilog MiniWorkshop,3,One of the verification setup (verilog only based),Test Harness,Verification does (in short) : Stimulation of hits, triggers, commands, precoded time relations Analysis of packets (in relation to Stimulations),tbInclude,DUT,The ABC verification environment,tests,tasks,Cloc

4、ks, fixed sequences,Sequence orders,Python Analysis,Analyser,14 Nov 2013,SystemVerilog MiniWorkshop,4,Joel de Witt UCSC F.A. CERN,The ABC verification environment,Algorithm Development Using Matlab and Cadence Incisive,14 Nov 2013,SystemVerilog MiniWorkshop,5,Michelle Key-Charriere RAL,The ABC verif

5、ication environment,Object Oriented Software Trace,Michelle Key-Charriere RAL,14 Nov 2013,SystemVerilog MiniWorkshop,6,SystemVerilog and UVM,MY starting point : the SystemVerilog training course .,(Sorry Mr. Fitch! It was a wonderful course!),14 Nov 2013,SystemVerilog MiniWorkshop,7,SystemVerilog an

6、d UVM,And later on about UVM . (from an Accelera course slide),YES !,?,14 Nov 2013,SystemVerilog MiniWorkshop,8,SystemVerilog and UVM,At least I have seen the interest of THIS feature in SV/UVM :$RANDOM !In the spirit of SV, this has to do with test & functionality coverage, through generation of ra

7、ndom data and address sets.For exp. systems the feature becomes naturally useful as experiments have to deal with random (physics) data AND random triggers time distributions (with constraints ),14 Nov 2013,SystemVerilog MiniWorkshop,9,So generating random physics data set is an easy trickrand int u

8、nsigned hit; constraint Hits (hit dist 0,255;)for (int i=0;i256;i+) beginif (i = hit) hitbusi = 1;elsehitbusi = 0;end,SystemVerilog and UVM,transaction,driver,14 Nov 2013,SystemVerilog MiniWorkshop,10,SystemVerilog and UVM,transaction,sequencer,What about getting a fix pattern data ?rand bit 57:0 co

9、m0; constraint busy0 com07:0 dist 0:255; constraint busy1 com015:8 dist 0:255; Data = 4h3, 4h0, 4h0, 4h0, 4h1, 4hf, 3h0,LEFT, 4h1; uvm_do_with (req, com057:0 = HEADER, HCCField, HCCID, ABCID, RegAdress, WRITE, Data ; start_data 100;),Com0 is 58 bits word : 258 = 288230376151711744, seems beyond SV l

10、imits,14 Nov 2013,SystemVerilog MiniWorkshop,11,UVM for the ABC verification,Transaction !,What appeared is that UVM is a sort of wrapper formalism for SystemVerilog,UVM is a METHODOLOGY,Predefined list of filesPreformatted files contents,14 Nov 2013,SystemVerilog MiniWorkshop,12,UVM for the ABC ver

11、ification,For ABC the interest is in running parallel transactions,sequence,driver,agent,L0COM interface,sequence,driver,agent,interface,sequence,driver,agent,sequencers,env,test,DUT,Hit,L0,COM,sequence,driver,agent,sequence,driver,agent,R3L1interface,L1,R3,14 Nov 2013,SystemVerilog MiniWorkshop,13,

12、transaction,transaction,transaction,transaction,transaction,UVM for the ABC verification,HitBus_if si (clk); ABCDriveCOML0_if comL0_si (clk); ABCDriveR3L1_if R3L1_si (clk);,ABC_top.sv (module),task main_phase(uvm_phase phase); phase.raise_objection(this);begin/ create and start the virtual sequencev

13、irtual_seq vseq;vseq = virtual_seq:type_id:create();vseq.start(m_env.m_virtual_seqr);endphase.drop_objection(this); endtask: main_phase,ABC_test1.sv (class),ABC_env.sv (class),m_virtual_seqr.HitBus_seqr = m_HitBus_agent.m_sequencer; m_virtual_seqr.COM_seqr = m_COM_agent.m_sequencer; m_virtual_seqr.L

14、0_seqr = L0_agent.m_sequencer; m_virtual_seqr.L1_seqr = L1_agent.m_sequencer;,14 Nov 2013,SystemVerilog MiniWorkshop,14,UVM for the ABC verification,virtual ABCDriveCOML0_if vif;m_driver.L0_si = vif;m_driver.seq_item_port.connect(m_sequencer.seq_item_export);,L0_agent.sv (class),virtual ABCDriveCOML

15、0_if.senderL0 L0_si;virtual task drive_L0_trans (ABCDriveL0_transaction tl0);drive_L0 (tl0.L0, 2*bit_period*tl0.L0_dist); endtask : drive_L0_transseq_item_port.get(tl0); / Getdrive_L0_trans(tl0); / and Drive,L0_Driver.sv (class),. . .,. . .,. . .,Same (similar) class definitions for the 3 other tran

16、sactions (L1, com, Hit),Interface decl.,Seq. to Drive connection,Transaction, interval,Get and Drive,14 Nov 2013,SystemVerilog MiniWorkshop,15,UVM for the ABC verification,L1_sequence.sv (class),task body; / Does L1 selection within countfor (int i=0; i=count;i+) beginL1val = L1val+1;$display (“L1va

17、l = t %b, count = t %b“, L1val7:0, i); uvm_do_with (req, L1C10:0 = HEADER, L1val ; L1_dist = $dist_exponential(1,400);) end,Number of L1 sequences,11bits sequence, 3 bits Header, 8 bits binary count number, Interval btw. sequences with exponential distribution,14 Nov 2013,SystemVerilog MiniWorkshop,

18、16,UVM for the ABC verification,L1_transaction.sv (class),rand bit 10:0 L1C;constraint busy9 L1C dist 0:2047; rand bit pick_L1; / Select First Level Trigger signalconstraint busy10 pick_L1 dist 0 :/ 9, 1 :/ 1; / 10% at 1rand int unsigned L1_dist;constraint val1 L1_dist dist 200:400; ,Variables decla

19、rations with constraints,14 Nov 2013,SystemVerilog MiniWorkshop,17,UVM for the ABC verification,Hit,COM,L0,L1,14 Nov 2013,SystemVerilog MiniWorkshop,18,UVM for the ABC verification,Hit,COM,L0,L1,14 Nov 2013,SystemVerilog MiniWorkshop,19,Development plans,Develop the control & input sequences close t

20、o real case Join with the existing setup for ABC+HCC system, developed at RAL by M. Key-Charriere Explore the random nature of stimuli to verify/validate the response of the ABC/HCC to false commands, bit errors, disordered triggers etc ,14 Nov 2013,SystemVerilog MiniWorkshop,20,SV/UVM for ABC syste

21、m ?,Could I have described the same sequences with std. verilog ? My experience : a veeery looooong training process UVM methodology saved me : I think I could not do the job with SystemVerilog without the UVM formalism The monitor/checker options did not look so attractive, however I did not do much work there Pay off for the effort . ?,14 Nov 2013,SystemVerilog MiniWorkshop,21,