IEEE C62 35-2010 en Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components《雪崩结半导体电涌保护器件试验规范》.pdf
《IEEE C62 35-2010 en Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components《雪崩结半导体电涌保护器件试验规范》.pdf》由会员分享,可在线阅读,更多相关《IEEE C62 35-2010 en Standard Test Methods for Avalanche Junction Semiconductor Surge-Protective Device Components《雪崩结半导体电涌保护器件试验规范》.pdf(26页珍藏版)》请在麦多课文档分享上搜索。
1、g44g40g40g40g3g54g87g71g3g38g25g21g17g22g24g140g16g21g19g20g19g11g53g72g89g76g86g76g82g81g3g82g73g44g40g40g40g3g54g87g71g3g38g25g21g17g22g24g16g20g28g27g26g12g44g40g40g40g3g54g87g68g81g71g68g85g71g3g55g72g86g87g3Mg72g87hg82dg86g73g82g85g3g36g89g68g79g68g81g70g75g72g3g45g88g81g70g87g76g82g81g3g54g72g
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3、2g3g39g72g89g76g70g72g86g3g38g82g80g80g76g87g87g72g72g44g40g40g40g22g3g51g68g85g78g3g36g89g72g81g88g72g3g49g72g90g3g60g82g85g78g15g3g49g60g3g20g19g19g20g25g16g24g28g28g26g15g3g56g54g36g3g3g22g20g3g36g88g74g88g86g87g3g21g19g20g19g38g25g21g17g22g24g55g48IEEE Std C62.35- 2010(Revision ofIEEE Std C62.35
4、-1987)IEEE Standard Test Methodsfor Avalanche Junction Semiconductor Surge-Protective Device ComponentsSponsorSurge Protective Devices Committeeof theIEEE Power for example, failure in the short-circuit fault mode. However, system objectives of other users can require that a particular device should
5、 failin an open-circuit fault mode in order to achieve the desired performance of the system.Thus, failure in the short-circuit fault mode, while considered “fail-safe” by many users, may in fact beconsidered just the opposite by other users. Therefore, the recommended practice is to describe the fa
6、ilure byone of the modes defined above.The device may be equipped with a mechanism that becomes short circuited at an extreme or abnormallyhigh temperature condition. 8. Derived parameters and other test procedures.8.1 Breakdown voltage (V(BR) test (See Figure 5)The purpose of this test is to determ
7、ine the breakdown voltage of an ABD at a specified current level. Apulse of specified width and breakdown current, IT, amplitude shall be applied and the stabilized value ofbreakdown voltage, V(BR), measured near the pulse. The heating effect of this test should not change themeasured voltage by mor
8、e than the accuracy of the voltage measurement. In the absence of specialrequirements, it is recommended a 1 mA test current, IT, with a pulse width of less than 400 ms be used forbreakdown voltages higher than 8 V. Lower breakdown voltage devices may use a higher test current, IT, of10 mA and a cor
9、respondingly reduced current pulse width.This electrical characteristic is specified as a voltage range for the specified test conditions.PS Power supply (accurate pulsed current source for IT)A Track and hold ammeter DVMDigital voltmeter or oscilloscopeABDPS DVMAV(BR)ITIEEE Std C62.35-2010IEEE Stan
10、dard Test Methods for Avalanche Junction SemiconductorSurge-Protective Device Components11Copyright 2010 IEEE. All rights reserved.Figure 5Test circuit for verifying breakdown voltage (V(BR)8.2 Rated peak impulse power (PPPM)This parameter is the product of the peak pulse current multiplied by the c
11、lamping voltage. Determination ofthis parameter requires the simultaneous measurement of both peak pulse current and maximum clampingvoltage, which may not be coincident in time with the impulse current for any given waveform.8.3 Rated average power dissipation (PM(AV)This parameter is specified by
12、the manufacturer in order to limit device temperatures for reliable long life,taking into consideration two parameters:a) Average input current through the junction by repetitive transients, usually indicated by a dutycycle.b) The thermal resistance of the device to the environment by leads or heat-
13、sink mounting or both asrecommended by the manufacturer. Thermal resistance is usually expressed as K/W with C/W asan alternative.8.4 Capacitance (C, CJ) The capacitance shall be measured at a specified signal level, frequency, and bias voltage. NOTEIn the absence of a specific requirement, a signal
14、 level of 10 mV RMS, a frequency of 1 MHz and a DC bias ofzero are recommended for this test.8.5 Insertion loss This test is conducted to determine the loss of transmitted power at a specified frequency, or frequencyrange, caused by the insertion of an ABD into a circuit. It is important for any sys
15、tem carrying acommunication signal.8.5.1 General considerationsThe insertion loss measured for an ABD is strongly dependent on the impedances of the source and the load,and on frequency. Insertion loss specified for an ABD shall therefore include a description of the source andload impedances, as a
16、function of frequency. The range of frequencies over which the measurements aremade shall be suitable for the application.In selecting the impedances for the measurement, consider that the insertion loss in a specific applicationcould be significantly different from that specified for the device, if
17、 either the impedance of the source, orthe load, or both is different from those used in developing the device specification. Therefore theimpedances used in characterizing the insertion loss of the ABD should reflect the application. Incommunications circuits, the source and load impedances are gen
18、erally taken to be the characteristicimpedance of the cabling.The ABD shall be tested at the specified ambient temperature.A bias voltage or current can affect the capacitance of an ABD. If present in the application, a bias voltageshall be applied to the ABD.IEEE Std C62.35-2010IEEE Standard Test M
19、ethods for Avalanche Junction Semiconductor Surge-Protective Device Components12Copyright 2010 IEEE. All rights reserved.Figure 6Circuit for measuring insertion loss (see Clause 2)8.5.2 MeasurementNetwork analyzers can make measurements of insertion loss directly, without need for the calculation. I
20、fsuch equipment is not available the following procedure can be used.a) Set up the circuit as shown in Figure 6. Here the source is shown as having a voltage VSand animpedance ZS. The load impedance is shown as ZL. The source and the load impedance shall equalthe characteristic impedance of the syst
21、em.b) With the position X-Y as shown in Figure 6 open, measure VXY1at each specified frequency. Theninsert the ABD at position XY as shown in Figure 6, and measure the voltage VXY2at eachspecified frequency.c) Calculate the power for each measurement as follows:PXY1= (VXY1) / ZLPXY2= (VXY2) / ZLd) T
22、he insertion loss in decibels at each specified frequency is given by the formula:Insertion Loss = 10 log (PXY1/ PXY2)At frequencies over 1 MHz uncontrolled stray reactances in the test setup can reduce the accuracy of theinsertion loss measurement. IEEE Std C62.36-2000, describes Insertion Loss mea
23、surement methods (Figure 4, configuration 2B).8.6 Voltage overshoot (VOS) (See Figure 7)Overshoot voltage (VOS) is the peak voltage (V1) minus the clamping voltage (VC) of the ABD. This highervoltage is referred to as “overshoot”. This overshoot is primarily attributable to the inductance, LS, of th
24、eABD packaging.Thus, measurements of clamping voltage at steep front and high peak currents shall include steps to reduceerrors due to measurement circuit lead length and loop coupling.ZSVSZLXYSource TestPositionVoltageMeasuringInstrumentVXYIEEE Std C62.35-2010IEEE Standard Test Methods for Avalanch
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