JEDEC JESD89-2A-2007 Test Method for Alpha Source Accelerated Soft Error Rate.pdf

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1、JEDEC STANDARD Test Method for Alpha Source Accelerated Soft Error Rate JESD89-2A Addendum No. 2 to JESD89 (Revision of JESD89-2, November 2004) OCTOBER 2007 (Reaffirmed: JANUARY 2012)JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prep

2、ared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitati

3、ng interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are a

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5、 included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and

6、ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address bel

7、ow, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees n

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10、 907-7559 JEDEC Standard No. 89-2A Page 1 TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE (From JEDEC Board Ballot JCB-07-88, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This test method is offered as standardized pr

11、ocedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) by measuring the error rate while the device is irradiated by a characterized, solid alpha source The results of this accelerated test can be

12、used to estimate the alpha particle induced SER for a given alpha radiation environment. JESD89 describes considerations for executing such an estimate from data collected with this test method. Refer to JESD89 for other background on the motivation for requirements in this test method and guidance

13、for those elements left to the discretion of the tester. NOTE 1 This test cannot be used to project cosmic-ray induced SER. NOTE 2 Special considerations apply to devices that are more than memory arrays and/or bistable logic elements. These can preclude the application of this test procedure. Refer

14、 to JESD89 for further discussion on some examples. 1.1 Applicable documents JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices JESD89-1 Test Method for Real-Time Soft Error Rate JESD89-3 Test Method for Beam Accelerated Soft E

15、rror Rate JEDEC Standard No. 89-2A Page 2 2 Apparatus The performance of this test requires equipment that is capable of providing the particular test conditions to which the test samples will be subjected. 2.1 Vehicle design and operation The biasing and operating schemes shall consider the limitat

16、ions of the devices and shall not overstress the devices or contribute to thermal runaway. 2.2 Device mounting Equipment design, if required, shall provide for mounting of devices to minimize adverse effects while parts are under test (e.g., improper heat dissipation). 2.3 Power supplies and signal

17、sources Instruments (e.g., oscilloscopes) used to set up and monitor power supplies and signal sources shall be calibrated and have long-term stability. Electrical noise shielding shall be in place to allow for accurate test results. 3 Terms and definitions DUT: Device under test. absolute maximum r

18、ated voltage: The maximum voltage that may be applied to a device and beyond which damage (latent or otherwise) may occur. It is frequently specified by device manufacturers for a specific device and/or technology. alpha activity (of a source): The number of alpha particles that decay in an alpha so

19、urce per unit time. NOTE The preferred SI unit is the becquerel (Bq), which is one disintegration per second. (1 curie = 3.7 x 1010becquerels). critical charge (Qc): The minimum amount of collected charge that will cause the node to change state. JEDEC Standard No. 89-2A Page 3 3 Terms and definitio

20、ns (contd) flux density (of particle radiation): The time rate of flow of radiant-energy particles emitted from or incident on a surface, divided by the area of that surface. NOTE 1 The equation “flux density = N/At” applies, where N, A, and t represent the quantities number of particles, area, and

21、time. NOTE 2 The unit symbol (e.g., cm-2s-1) does not identify particle type. The particle name may be placed before the term, e.g., “neutron flux density”, or in the spelled-out unit name, e.g., “neutrons per square centimeter second”. NOTE 3 Flux density is maximized when the surface is perpendicu

22、lar to the direction of the incident particle flow. hard error: An irreversible change in operation that is typically associated with permanent damage to one or more elements of a device or circuit (e.g., gate oxide rupture, destructive latch-up events) NOTE The error is called “hard” because the da

23、ta is lost and the circuit or device no longer functions properly, even after power reset and re-initialization. maximum operating voltage: The maximum supply voltage at which a device is specified to operate in compliance with the applicable device specification or data sheet. minimum operating vol

24、tage: The minimum supply voltage at which a device is specified to operate in compliance with the applicable device specification or data sheet. multiple-bit upset (MBU): A multiple-cell upset (MCU) in which two or more error bits occur in the same word. NOTE An MBU cannot be corrected by a simple (

25、single-bit) ECC. multiple-cell upset (MCU): A single event that induces several bits in an IC array to fail at the same time. NOTE The error bits are usually, but not always, physically adjacent. single-event burnout (SEB): An event in which a single energetic-particle strike induces a localized hig

26、h-current state in a device that results in catastrophic failure. single-event effect (SEE): Any measurable or observable change in state or performance of a microelectronic device, component, subsystem, or system (digital or analog) resulting from a single energetic-particle strike. NOTE Single-eve

27、nt effects include single-event upset (SEU), multiple-bit SEU (MBU), multiple-cell upset (MCU), single-event functional interrupt (SEFI), single-event latch-up (SEL), single-event hard error (SHE), single-event transient (SET), single-event burnout (SEB), and single-event gate rupture (SEGR). JEDEC

28、Standard No. 89-2A Page 4 3 Terms and definitions (contd) single-event functional interrupt (SEFI): A soft error that causes the component to reset, lock-up, or otherwise malfunction in a detectable way, but does not require power cycling of the device (off and back on) to restore operability, unlik

29、e single-event latch-up (SEL), or result in permanent damage as in single-event burnout (SEB). NOTE An SEFI is often associated with an upset in a control bit or register. single-event gate rupture (SEGR): An event in which a single energetic-particle strike results in a breakdown and subsequent con

30、ducting path through the gate oxide of a MOSFET. NOTE An SEGR is manifested by an increase in gate leakage current and can result in either the degradation or the complete failure of the device. single-event hard error (SHE): An irreversible change in operation resulting from a single radiation even

31、t that is typically associated with permanent damage to one or more of a device (e.g., gate oxide rupture). single-event latch-up (SEL): An abnormal high-current state in a device caused by the passage of a single energetic particle through sensitive regions of the device structure and resulting in

32、the loss of device functionality. NOTE 1 SEL may cause permanent damage to the device. If the device is not permanently damaged, power cycling of the device (off and back on) is necessary to restore normal operation. NOTE 2 An example of SEL in a CMOS device occurs when the passage of a single parti

33、cle induces the creation of parasitic bipolar (p-n-p-n) shorting of power to ground. single-event transient (SET): A momentary voltage excursion (voltage spike) at a node in an integrated circuit caused by the passage of a single energetic particle. single-event upset (SEU): A soft error caused by t

34、he signal induced by the passage of a single energetic particle. soft error, device: An erroneous output signal from a latch or memory cell that can be corrected by performing one or more normal functions of the device containing the latch or memory cell. NOTE 1 As commonly used, the term refers to

35、an error caused by radiation or electromagnetic pulses and not to an error associated with a physical defect introduced during the manufacturing process. NOTE 2 Soft errors can be generated from SEU, SEFI, MBU, MCU, and/or SET. The term SER, which includes a variety of soft error mechanisms, has bee

36、n adopted by the commercial industry while the more specific terms SEU, SEFI, etc. are typically used by the avionics, space, and military electronics communities. soft error, power cycle (PCSE): A soft error that is not corrected by repeated reading or writing but can be corrected by the removal of

37、 power (e.g., nondestructive latch-up). JEDEC Standard No. 89-2A Page 5 3 Terms and definitions (contd) soft error, static: A soft error that is not corrected by repeated reading but can be corrected by rewriting without the removal of power. soft error, transient: A soft error that can be corrected

38、 by repeated reading without rewriting and without the removal of power. 4 Procedure 4.1 Test duration The test duration shall be specified by internal qualification requirements or the applicable procurement document. The test duration may be specified as the length of time to observe a minimum num

39、ber of errors. The test duration is defined as the time from the first test data write to the last test read. For static tests with test voltage above the maximum operating voltage or below the minimum operating voltage, the test write and read shall be performed at nominal voltage; immediately afte

40、r the test write, the voltage shall be changed to the test voltage, and immediately before the test read, the voltage shall be changed to the nominal voltage. Care shall be taken not to induce any errors while changing the voltage. The alpha source shall be placed before the first data write and sha

41、ll remain in place until after the final read. 4.2 Test conditions 4.2.1 Test voltage Unless otherwise specified, the test voltage shall be the nominal operating voltage specified for the device. In order to characterize alpha particle SER as a function of Qcrit, lower and higher voltages are also p

42、ermitted. The test voltage shall not exceed the absolute maximum rated voltage for the device and shall be agreed upon by the device manufacturer. 4.2.2 Biasing configurations Device outputs may be unloaded or loaded to achieve the specified output voltage level. If a device has a thermal shutdown f

43、eature, it shall not be biased in a manner that could cause the device to go into thermal shutdown. JEDEC Standard No. 89-2A Page 6 4.2 Test conditions (contd) 4.2.1 Test voltage (contd) 4.2.2.1 Alpha source accelerated SER test Unless otherwise stated, the alpha source accelerated SER test shall be

44、 configured to provide write/read function to the entire available memory array or sensitive bistable circuit area of the device samples with insitu pass fail recording. Unless otherwise specified, the patterns or pattern suite shall consist of an equal mix of physical 1s and 0s for memory elements;

45、 this may not apply to bistable logic elements which are architected to have preferential data states. For bistable logic circuits, data shall be collected on each circuit element. For example, data collection is required to quantify the master and slave elements of a flip-flop circuit separately. F

46、urthermore, it is recommended that the patterns or pattern suite approximate typical use. For characterization purposes test conditions can be modified. These include supply voltages, clock frequencies, input signals, etc. which may be operated outside their specified values. When operating outside

47、the application range of the part, predictable and nondestructive behavior of the devices under test shall be assured. NOTE A preferred alpha source material may depend on expectations about the alpha source species and its physical distribution in the product of interest. Refer to JESD89 for guidan

48、ce on these considerations. (1) Am and Th are common source species for testing; they are employed frequently to simulate Po-based decay from Pb packaging and U- and Th-based decay from a variety of mined materials, respectively. Test results should be expected to vary as function of source species.

49、 (2) Distribution of the alpha source in the packaged product can influence the preferred energy spectrum for the test alpha source. A thin-film source is often used to simulate a layer of surface contamination. A test source with a distributed energy spectrum is often used to simulate alpha emission from bulk materials. 4.3 Test sequence A minimal test sequence shall include: 1) Test readiness check (see 4.3.1) 2) Load DUT and place alpha source 3) Initial DUT test 4) Collect data 5) Final test (see 4.3.2) 6) Repeat steps 1 though 5 for additional parts JEDEC Standard No. 89-2A