JEDEC JESD8-25-2011 POD10 1 0 V PSEUDO OPEN DRAIN INTERFACE.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD825SEPTEMBER 2011JEDECSTANDARDPOD10 1.0 V PSEUDO OPENDRAIN INTERFACE NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby t

2、he JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum

3、delay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processes. By such a

4、ction JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach toproduct specification and application, principall

5、y from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requirements stated

6、in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 9077559 orwww.jedec.orgPublished byJEDEC Solid State Technology Association 20093103 North 10th StreetSuite 240 S

7、outhArlington, VA 222012107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting material.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards an

8、d Publications online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to reproduce a

9、 limited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 9077559JEDEC Standard No. 8-25Page 1POD10 - 1.0 V PSEUDO OPEN DRAIN INTERFACE(From JEDEC Boar

10、d Ballot JCB-11-45, formulated under the cognizance of the JC-16 Committee on Inter-face Technology.)1 ScopeThis document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that,

11、 when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Although this specification is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD10 compliant devices. Ph

12、ysics dictates variations in output driver characteristics and termination values in different interconnect network topologies. Drivers and terminators appropriate in a point-to-point interconnect scheme are not necessarily suitable in a multi-drop bus application. Multiple Classes of POD10 are expe

13、cted to reside within the family of POD10 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD10 are documented in the appendices of this document (e.g. POD10/Class A, POD10/Class B, POD10/Class C, etc.)In all cases, dr

14、ivers and terminators are expected to produce a roughly symmetric swing about the input trip-point of POD10 receivers. Unlike the signals on other interfaces, such as HSTL, that are designed to produce signals that swing symmetrically about VDDQ/2, the signals on a POD10 interconnect line are not ge

15、nerally expected to pull to VSS. POD10 input buffers are generally expected to be supported by pull-up-only parallel input termination. POD10 output drivers are therefore expected to demonstrate an asymmetric output drive impedance. In point-to-point applications, for example, if the output drivers

16、were expected to demonstrate a nominal 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance.The core of this standard defines the dc and ac single-ended and differential operating conditions for POD10 input buffers as well as the t

17、erms and definitions necessary to describe the characteristics and behavior of output drivers. Section 2 in this document documents the subset of values common to all Classes of POD10 and documents specification items left to definition within a specific Class. The values specific to each particular

18、 class of POD10 are found in the appendices. (Note it does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD10. Multiple Classes may reuse a given specification value if appropriate to the Class requireme

19、nts.)Inasmuch as additional classes may be added to this specification at the will of the authorizing committee and the JEDEC Board of Directors, the reader is advised to check the JEDEC website (http:/www.jedec.org) for the latest release of the specification.JEDEC Standard No. 8-25Page 22 Core POD

20、10 interface specificationsTable 2-1 DC operating conditionsParameter SymbolPOD10Unit NoteMin Typ MaxDevice Supply Voltage VDD n/a n/a n/a V 1Output Supply Voltage VDDQ CDV 1.0 CDV V 2Reference Voltage VREF CDV CDV CDV V 3DC Input Logic HIGH Voltage VIH (DC) CDV CDV VDC Input Logic LOW Voltage VIL (

21、DC) CDV CDV VInput Leakage CurrentAny Input 0 V = VIN= VDDQ(All other pins not under test = 0 V) Il A 4Output Leakage Current (DQs are disabled; 0 V = Vout = VDDQ)Ioz A 4Output Logic LOW Voltage VOL (DC) 0.42 VNOTE 1 The POD10 interface may be implemented on any device without regard to VDD. Althoug

22、h VDD can generally be expected to greater than or equal to VDDQ, compliant devices may support VDD values lower than VDDQ.NOTE 2 POD10 compliant devices are expected to tolerate PCB designs with separate VDD and VDDQ power regulators.NOTE 3 The source of Reference Voltage and control of Reference V

23、oltage, and association of Reference Voltage with specific I/O pins may be determined control mechanisms specified by the device vendor.NOTE 4 These parameters are expected to be standardized by product type and are therefore left blank intentionally here.Notice: CDV means Class Dependent Value. See

24、 specific Class tables for further details.Table 2-2 AC operating conditionsParameter SymbolPOD10Unit NoteMin Typ MaxAC Input Logic HIGH Voltage VIH (AC) CDV VAC Input Logic Low Voltage VIL (AC) CDV VNotice: CDV means Class Dependent Value. See specific Class tables for further details.JEDEC Standar

25、d No. 8-25Page 32 Core POD10 interface specifications (contd)VIL (AC)VIL (DC)VREF DC NoiseVREF DC NoiseVREF + DC NoiseVREF + AC NoiseVIH (DC)VIH (AC)VOHVIN (AC) Provides marginbetween VOL (MAX) andVIL (AC)VOL (MAX)System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation)OutputInput

26、Figure 2-1 Voltage waveformJEDEC Standard No. 8-25Page 42 Core POD10 interface specifications (contd)Table 2-3 Differential input operating conditionsParameter SymbolPOD10Unit NoteMin MaxDif Input Mid-Point Voltage; Pin and Pin# VMP (DC) CDV CDV V 1Dif Input Differential Voltage; Pin and Pin# VID (D

27、C) CDV V 1, 3Dif Input Differential Voltage; Pin and Pin# VID (AC) CDV V 1, 2, 3Single-ended Input Voltage; Pin and Pin# VIN CDV CDV V 1Single-ended Input Voltage Slew Rate; Pin and Pin# VINS CDV V/ns 4Dif Input Crossing Point Voltage; Pin and Pin# VIX (AC) CDV CDV V 2Allowed time before ringback to

28、 VID (AC) tDVACps 2, 9NOTE 1 “Pin” and “Pin#” represent the true and compliment pins of a differential input pair.NOTE 2 For AC operations, all DC requirements must be satisfied as well.NOTE 3 VID is the magnitude of the difference between the input level in Pin and the input level on Pin#.NOTE 4 Th

29、e slew rate is measured between VREF crossing and VIX (AC).NOTE 5 The Pin and Pin# input reference level (for timing referenced to Pin and Pin#) is the point at which Pin and Pin# cross. NOTE 6 Figure 2-3: illustrates the exact relationship between (Pin-Pin#) and VID(AC), VID(DC) and tDVACNOTE 7 Rin

30、gback voltage on Pin or Pin# below VID(DC) is not allowed.NOTE 8 tDVACis not measured in and of itself as a compliance specification, but is relied upon in measurement of Pin operating conditions and Pin related parameters.NOTE 9 This parameter is expected to be standardized by product type and is t

31、herefore left blank intentionally here.Notice: CDV means Class Dependent Value. See specific Class tables for further details.JEDEC Standard No. 8-25Page 52 Core POD10 interface specifications (contd)VIX(AC)Pin#PinMaximum Input LevelMinimum Input LevelVID (AC)VID (DC)VMP (DC)Figure 2-2 Pin waveformJ

32、EDEC Standard No. 8-25Page 62 Core POD10 interface specifications (contd)0VID (AC) MINtDVACtDVAChalf cycletimeDifferentialInputVoltage(i.e.V(Pin) V(Pin#)VID (DC) MIN(VID (DC) MIN)(VID (AC) MIN)Figure 2-3 Definition of differential ac-swing and “time above ac-level” tDVACThe Driver and Termination im

33、pedances should be characterized under the following test conditions:1) Set VDDQ to Nominal.2) Power the compliant device and calibrate the output drivers and termination to eliminate process variation at 25 C.3) Reduce temperature to the device low operating temperature limit plus 10 C and recalibr

34、ate.4) Reduce temperature to low operating temperature limit and take the fast corner measurement.5) Raise temperature to the device high operating temperature limit minus 10 C and recalibrate.6) Raise temperature to high operating temperature limit and take the slow corner measurement.7) Reiterate

35、2 to 6 with VDDQ at Max limit.8) Reiterate 2 to 6 with VDDQ at Min limit.JEDEC Standard No. 8-25Page 73 Drive strength and termination issuesInasmuch as the POD10 interface can be useful for interconnecting many sorts of high speed devices, operating in significantly divergent price/performance and

36、power domains, compliant devices are not required to offer on-die input termination. Nevertheless on-die input termination is expected to be the norm for POD10 compliant devices.In order to achieve sufficient precision in drive strength and termination impedance over process, temperature and voltage

37、 variations, compliant devices are generally expected to implement some sort of impedance control scheme on output drivers and on-die input terminators, if present. Best practices dictate drivers and terminators maintain their target impedance (+/- 20% or better) over a voltage of VDDQ * 0.20 to VDD

38、Q * 0.80. Specific device types with particular interface speed requirements are expected to establish specific control schemes and precision requirements within the POD10 framework that are appropriate to their target applications.JEDEC Standard No. 8-25Page 8Annex A (normative) POD10/Class APOD10/

39、Class A is intended for point-to-point interconnect applications.Table A-1 DC operating conditionsParameter SymbolPOD10Unit NoteMin Typ MaxDevice Supply Voltage VDD n/a n/a n/a V 1Output Supply Voltage VDDQ 0.97 1.0 1.03 V 2Reference Voltage VREF 0.69 * VDDQ0.70 * VDDQ0.71 * VDDQ V 3, 4DC Input Logi

40、c HIGH Voltage VIH (DC) VREF + 0.07 VDDQ + 0.12 VDC Input Logic LOW Voltage VIL (DC) -0.12 VREF - 0.07 VInput Leakage CurrentAny Input 0V = VIN= VDDQ(All other pins not under test = 0V) Il A 5Output Leakage Current (DQs are disabled; 0V = Vout = VDDQ)Ioz A 5Output Logic LOW Voltage VOL (DC) 0.42 VNO

41、TE 1 The POD10 interface may be implemented on any device without regard to VDD. Although VDD can generally be expected to greater than or equal to VDDQ, compliant devices may support VDD values lower than VDDQ.NOTE 2 POD10 compliant devices are expected to tolerate PCB designs with separate VDD and

42、 VDDQ power regulators.NOTE 3 The design of POD10 anticipates boards that use POD10 compliant devices will control AC noise to 50 mV pk-pk or less.NOTE 4 The source of Reference Voltage and control of Reference Voltage, and association of Reference Voltage with specific I/O pins may be determined co

43、ntrol mechanisms specified by the device vendor.NOTE 5 These parameters are expected to be standardized by product type and are therefore left blank intentionally here.Table A-2 AC operating conditionsParameter SymbolPOD10Unit NoteMin Typ MaxAC Input Logic HIGH Voltage VIH (AC) VREF + 0.13 VAC Input

44、 Logic Low Voltage VIL (AC) VREF - 0.13 VJEDEC Standard No. 8-25Page 9Annex A (normative) POD10/Class A (contd)Table A-3 Differential input operating conditionsParameter SymbolPOD10Unit NoteMin MaxDif Input Mid-Point Voltage; Pin and Pin# VMP (DC) VREF - 0.07 VREF + 0.07 V 1Dif Input Differential Vo

45、ltage; Pin and Pin# VID (DC) 0.14 V 1, 3Dif Input Differential Voltage; Pin and Pin# VID (AC) 0.26 V 1, 2, 3Single-ended Input Voltage; Pin and Pin# VIN 0.23 VDDQ + 0.12 V 1Single-ended Input Voltage Slew Rate; Pin and Pin# VINS 3 V/ns 4Dif Input Crossing Point Voltage; Pin and Pin# VIX (AC) VREF -

46、0.07 VREF + 0.07 V 2Allowed time before ringback to VID (AC) tDVACps 2, 9Notes:NOTE 1 “Pin” and “Pin#” represent the true and compliment pins of a differential input pair.NOTE 2 For AC operations, all DC requirements must be satisfied as well.NOTE 3 VID is the magnitude of the difference between the

47、 input level in Pin and the input level on Pin#.NOTE 4 The slew rate is measured between VREF crossing and VIX (AC).NOTE 5 The Pin and Pin# input reference level (for timing referenced to Pin and Pin#) is the point at which Pin and Pin# cross. NOTE 6 Figure 2-3: illustrates the exact relationship be

48、tween (Pin-Pin#) and VID(AC), VID(DC) and tDVACNOTE 7 Ringback voltage on Pin or Pin# below VID(DC) is not allowed.NOTE 8 tDVACis not measured in and of itself as a compliance specification, but is relied upon in measurement of Pin operating conditions and Pin related parameters.NOTE 9 This paramete

49、r is expected to be standardized by product type and is therefore left blank intentionally here.JEDEC Standard No. 8-25Page 10Rev. 9/02 Standard Improvement Form JEDEC The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publicatio