JEDEC JESD28-1-2001 N-Channel MOSFET Hot Carrier Data Analysis《N信道MOSFET热载体数据分析》.pdf

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1、 JEDEC STANDARD N-Channel MOSFET Hot Carrier Data Analysis JESD28-1 SEPTEMBER 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and

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10、call (703) 907-7559 JEDEC Standard No. 28-1 -i- N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS CONTENTS 1 Scope 1 2 Applicable Standards 1 3 Terms and Defintions 1 4 Measurement conditions and parameters 2 5 Dat requirements 3 6 Analysis methodologies 3 Figures 1 Example data for substrate/drain current

11、 ratio method 5 2 Example data for drain-source voltage acceleration method 6 3 Example data for the substrate current method 8 JEDEC Standard No. 28-1 -ii- JEDEC Standard No. 28-1 Page 1 N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS (From JEDEC Board Ballot JCB-01-47, formulated under the cognizance o

12、f the JC-14.2 Subcommittee on Wafer-Level Reliability.) 1 Scope The purpose of this addendum is to provide data analysis examples that may be useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum is not a standard but a reference that suggests possible alternative

13、hot-carrier data analysis techniques. The examples presented in this document are restricted to dc testing. While devices are often operated under ac or pulsed conditions, it is beyond the scope of this addendum to predict ac degradations or dc lifetimes of integrated circuits. The described analysi

14、s examples are restricted to devices of a single gate length and temperature. Characterization of a semiconductor process over a wide range of gate lengths and temperatures, is implemented by repeated use of the analysis techniques described within this addendum. 2 Applicable standards JESD-28, A Pr

15、ocedure for Measuring N-Channel MOSFET Hot-Carrier Induced Degradation Under DC Stress JESD-60, A Procedure for Measuring P-Channel MOSFET Hot-Carrier Induced Degradation at Maximum Gate Current Under DC Stress JESD-77A, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelect

16、ronic Devices 3 Terms and definitions 3.1 MOSFET Drain Stress Voltage (VDS,stress) The voltage that is applied between the drain contact and the source contact of a MOSFET during stress. 3.2 MOSFET Gate Stress Voltage (VGS,stress) The voltage that is applied between the gate contact and the source c

17、ontact of a MOSFET during stress. 3.3 MOSFET Drain Stress Current (ID,stress) The current at the drain contact under the MOSFET stress bias conditions VDS,stress and VGS,stress. JEDEC Standard No. 28-1 Page 2 3 Terms and definitions (contd) 3.4 MOSFET Substrate Stress Current (IB,stress) The current

18、 at the bulk contact under the MOSFET stress bias conditions VDS,stressand VGS,stress. 3.5 MOSFET Drain Voltage at Usage Condition (VDS,use) The drain voltage for the technology under worst case operating condition. 3.6 MOSFET Gate Voltage at Usage Condition(VGS,use) The worst-case degradation gate

19、voltage at VDS,use(See JESD-28). 3.7 MOSFET Drain Current at Usage Condition (ID,use) The current at the drain contact under the MOSFET usage bias conditions VDS,useand VGS,use. 3.8 MOSFET Substrate Current at Usage Condition (IB,use) The current at the bulk contact under the MOSFET usage bias condi

20、tions VDS,useand VGS,use. 3.9 The Specified Failure Criterion (YTAR)The specified degradation failure criteria for a particular measured parameter. 3.10 Time to Reach the Specified Failure Criterion (tTAR)The elapsed time for the degradation in a particular measured parameter to reach the failure cr

21、iterion (TAR). 4 Measurement conditions and parameters It is assumed that the hot electron measurements have been performed according to JEDEC specification JESD-28. These analysis methods can be applied to degradations in linear transconductance (Gm), threshold voltage (Vt), linear drain current (I

22、Dlin), saturated drain current (IDsat) or other transistor parameters. 4.1 Stress and usage conditions The device is to be stressed using VDS,stressand VGS,stressand the measured parameters are ID,stressand IB,stress. ID,stressand IB,stress are the initial values of these parameters and are measured

23、 at time equal zero during stress test. It is also necessary to measure the usage conditions for the MOSFET. In this case the applied bias conditions are VDS,useand VGS,useand the measured parameters are ID,useand IB,use. An identical applied nominal bulk voltage should be the used in both the stres

24、s and usage measurements. JEDEC Standard No. 28-1 Page 3 4.1 Stress and usage conditions (contd) It is preferable to perform all stressing measurements on transistors with identical widths. However, it is sometimes necessary to relate degradations in test transistors of various widths. For this reas

25、on, the transistor width W parameter is displayed in most model equations and is not combined with other constants. 5 Data requirements Data collection methods are described in Section 6 of JESD-28. For n-channel MOSFET devices the degradation data typically displays power law behavior where the abs

26、olute value of the percentage change Y(t) in a parameter as a function of time t is given by: |Y(t)| = Ctn(1) A linear regression of log(|Y(t)|) versus log(t) provides the fit coefficients n and C. The time to failure tTARof each stressed transistor can be determined by algebraically rearranging Equ

27、ation 1 to give: tYCtarTARn=1/(2) where YTARis the specified degradation failure criteria. This process is repeated for each stressed transistor, and an individual value tTARdetermined. NOTE LDD devices can saturate during stress and this possibility should be considered when performing data fits as

28、 noted in JESD-28. 6 Analysis methodologies There are three analysis methods commonly used. Each method has equal validity and are based on the same carrier heating model. In this model the probability of a carrier achieving enough energy to cause device damage is directly related to the exponent of

29、 the lateral electric field. Each analysis methodology involves the characterization of several transistors at various stress bias conditions. The objective is to predict the time for a certain parameter degradation at usage bias condition. The analysis methods are: Substrate/drain current ratio met

30、hod Drain-source voltage acceleration method Substrate current method Whichever method is chosen a 2-sided confidence interval (e.g. 80%) can be constructed about the data set. The confidence bounds will indicate the likelihood that repeating the experiment will produce result passing the use condit

31、ion requirement. (If the confidence interval is excessively large consider increasing the sample size of stressed units or the number of stress conditions.) These methods are described in detail . JEDEC Standard No. 28-1 Page 4 6.1 Substrate/drain current ratio method Stressing experiments are perfo

32、rmed on a number of transistors, each at different stress bias conditions. A minimum of three stress conditions, with at least five transistors per stress condition is required. For each transistor, the stress conditions are VDS,stressand VGS,stressand the following parameters are obtained: tTAR; YT

33、AR; ID,stress; IB,stress; ID,use; IB,useand n. The failure time model is given by mstressDstressBstressDtarIIHWIt=,(3) where H and m are fit parameters and W is the transistor width. If measurements are performed on transistors of equal width, then the quantity W can be combined with the fit paramet

34、er H. Rearranging Equation 3 gives: mstressDstressBstressDtarIIHWIt=,(4) Taking the logarithm of both sides of Equation 4 yields: =stressDstressBstressDtarIImHWIt,logloglog (5) A linear regression analysis is performed to obtain fit parameters H and m. Figure 1 displays a plot of this relationship.

35、According to theory, m should be 3, but values may vary depending on stress conditions and technology. In a stress experiment with typical stress bias voltage conditions, a moderate variation in IB,stress/ID, stressresults in a large variation in failure times, tTAR. The quantity on the left hand si

36、de of Equation 5 is thus dominated by the failure times tTARwith other terms relatively constant. Once the constants H and m are determined, the time to failure at usage condition is estimated using Equation 4 to give: museDuseBuseDusetarIIIHWt=,1(6) JEDEC Standard No. 28-1 Page 5 6.1 Substrate/drai

37、n current ratio method (contd) VDS,stress = 6.5V7.0V7.5V8.0VFigure 1 Example data for substrate/drain current ratio method log , t I W tar D stress log,IIB stressD stressJEDEC Standard No. 28-1 Page 6 6.2 Drain-source voltage acceleration method In this method the stress is performed on a number of

38、transistors, each at a different stress condition VDS,stressand VGS,stress. For each transistor, the time to reach the failure criteria is obtained (ttar): The time to failure is given by: ttBVtar oDS stress=exp,(7) where toand B are fit parameters. Figure 2 displays a typical plot showing this rela

39、tionship. Taking the natural logarithm of both sides of Equation 7 yields the following relationship: ln ln,ttBVtar oDS stress=+1(8) A linear regression analysis of Equation 8 yields the fit coefficients toand B. The failure time ttar,useat usage bias conditions is found by substituting VDS,usefor V

40、DS,stressin Equation 8. 1VD,stressFigure 2 Example data for drain-source voltage acceleration method log(tTAR) JEDEC Standard No. 28-1 Page 7 6.3 Substrate current method Again stress experiments are performed on a number of transistors, each at a different stress bias condition. For each transistor

41、, the stress conditions are VDS,stressand VGS,stressand the following parameters are obtained: ttar;IB,stressand IB,use.The time to failure is given by tCIWtarBstressb=,(9) where C and b are fit parameters, and W is the transistor width. Figure 3 displays this relationship. Taking the logarithm of b

42、oth sides of Equation 9 yields the following: log log log,tCbIWtarBstress= (10) Again a linear regression is performed on Equation 10 to obtain the fit coefficients C and b. The time to failure at usage bias conditions is found from tCIWtar useBuseb,=(11) where IB,use/W in brackets is the substrate current per unit width at the usage condition averaged over the number of stressed transistors. JEDEC Standard No. 28-1 Page 8 6.3 Substrate current method (contd) )Figure 3 Example data for the substrate current method log(tTAR) log,IWBstress