JEDEC JESD24-1985 Power MOSFET-s《MOSFET功率》.pdf
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1、b - - - - EIA JESD24 85 I 3234b00 0005508 b I .- . I I JEDEC STANDARD POWER MOSFETs No. 24 JEDEC Solid State Products Engineering Council ,EIA x JESD24 85 m 3234600 0005509 8 m NOTICE This JEDEC Standard or Publication contains material that has been prepared, progressively reviewed, and approved th
2、rough the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of p
3、roducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need: Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor s
4、hall the existence of such standards preclude their voluntary use by those other than IA members whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not their adoption may involve patents or articles, mate
5、rials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publicat ions. The information included in JEDEC Standards and Publications represents a sound approach to product specif
6、ication and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication. may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestions relative to ,the c
7、ontent of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. PRICE : $18.00 Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 Copy
8、right 1985 ELECTRONIC INDUSTRIES ASSOCIATION Printed in U.S.A. f -7 i - EIA JESD24 85 E 3234600 0005518 9 E , JEDEC Standard No, 24 10 DC VALUE, COMPONENT NO ALTERNATING- NO ALTERNATINQ, CWPONENT Id Idm R WTMEANSQUAFI E MAXIMUM (PEAK) VALUE OF VALUE OF 1 I ING ti I r I i I iD INSTANTANEOUS n PEAK) I
9、 - I LA WITH ALTERNATING -1 COMPONENT Figure B. Use of Letter Symbols (applies to any volta or curnnt temis). Symbol - Term Ia gate current, dc IaF forward gate current JaR reverse gate current IGSS rtverse gate current, dfain shorf-circuited to source lass F forward gate current, to source drain sh
10、ort-circuited IQSS R reverse gate current, drain short-circuited to source IS source current, dc Definition The direct current into the gate terminal. The direct current into the gate terminal with a forward gatemsource voltage applied. The direct current into the gate terminal with a reverst gate-s
11、ource voltage applied. The direct current into the gate terminal of a junction-gate field-effect transistor when the gate terminai is reverse biased with respect to the source terminal and the drain terminal is short- circuited to source terminai. The direct current into the gate terminal of an insu
12、lated. gate 6eld.effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to the source terminal. The direct current into the gate terminal of an insulated- gate field-effect transistor with ? reverse gate-source voltage applied and the drain terminal short
13、-circuited to the source terminal. The direct current into the (ource terminal, 6 EIA JESD24 85 3234600 0005519 O M JEDEC Standard No. 24 Symbol %uxl source cutoff cumnt DcBnition The direct current into the source terminal of a depletion= type transistor with a specified gateadrain voltage applied
14、to bias the device to the off-state. IS DS gero-gat e-voltage source current The direct current into the source terminal when the gate- drain voltage is zero. Note: This an an on-state current in a depletion-type device, an offYstate current in an enhancement4ype device. PT PT total nonreactive powe
15、r input to all terminals The sum of the products of the dc input currents and volt ages. The sum of the products of the instantaneous input currents and voltages. nonreactive power input, instantaneous total, to ali terminals The sma-signal resistance between drain and source terminals with a specif
16、ied gate-source voltage applied to bias the device to the on-state. small-signal drain- source on=state resistance rde(on) Nots: For a depletion-type device, the gate-source voltage may be zero. static drain-source on-state resistance The dc resistance between the drain source terminals with a speci
17、6ied gate-source voltage applied to bias the device to the on-state. Note: For a depletion-type device, the gate-source voltage mw be zero. (Refer to thermal resistance definition in Section 1.2). RB RdUA thermal resistance thermal resistance, case-to-ambient The thermal resistance (steady state) fi
18、om the device case to the ambient, . The sum of voltage turn-off delay time and voltage rise time, i.e., td(off)u + trua voltage tiirn90ff time turn-on time Synonym for current turn-on time (see Note 1). ton ton() current turn-on time The sum of current turn-on delay time and current rise time, i.e.
19、, td(on)i + tri. voltage turn-on time The sum of voltage turn-on delay time and voltage fall time, i.e., t,qonju + tiu. pulse duration . (formerly pulse time) The time interval between a reference point on the leading edge of a pulse waveform and a reference point on the trailing edge of the same wa
20、veform. Note: The two reference points are usually 90% of the steady-state amplitude existing before the leading edge. If the reference points are 50% points, the symbol t, and term average pulse duration should be used, Synonym for current rise time (see Note 1). tr tri rise time current rise time
21、The time interval during which the drain current changes from 10% to 90% of its peak on-state value, ignoring spikes that are not charge-carrier-induced. voltage rise time The time interval during which the drain voltage changes from 10% to 90% of its peak off-state value, ignoring spikes that are n
22、ot charge-carrier-induced. tti . current tail time The time interval following current fall time during which the drain current changes from 10% to 2% of its peak on- state value, ignoring spikes that are not charge=carrier- induced. The time interval between a reference point on the leading edge of
23、 a puIse waveform and a reference point on the trailing edge of the same waveform, with both reference points being 50% of the steadystate amplitude of the waveform existing after the leading edge, measured with respect to the steady-state amplitude existing before the leading edge. average puise du
24、ration (formerly pulse average time) j EIA JESD24 85 m 3234600 0005522 O m JEDEC Standard No. 24 Symbol Definition Note: If the reference points are not 50% points, the symbol t, and term pulse duration should be used. turn-off crossover time, (This ia a reserve symbol to be used if nee of to wiii c
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