JEDEC JESD22-C101F-2013 Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.pdf

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1、JEDEC STANDARD Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components JESD22-C101F (Revision of JESD22-C101E, December 2009) OCTOBER 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain ma

2、terial that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers a

3、nd purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standar

4、ds and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publ

5、ications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may

6、be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to

7、 JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2013 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however

8、 JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduc

9、ed without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-C101F -i- Test Method C101F (Revision of Test Met

10、hod C101E) TEST METHOD C101F FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC-DISCHARGE-WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS Introduction This standard describes a uniform method for establishing charged device model (CDM) electrostatic discharge (ESD) “withstand” thres

11、holds. The update allows tests to be partitioned across multiple samples. This revision enables testing to be done to limit cumulative related failures, and also aligns the testing of CDM to HBM in terms of testing flexibility. JEDEC Standard No. 22-C101F Test Method C101F -ii- (Revision of Test Met

12、hod C101E) JEDEC Standard No. 22-C101F Page 1 Test Method C101F (Revision of Test Method C101E) TEST METHOD C101F FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC-DISCHARGE-WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS (From JEDEC Board Ballot JCB-04-102, JCB-08-60, JCB-09-87, a

13、nd JCB-13-53 formulated under the cognizance of the JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope All packaged semiconductor components, thin film circuits, surface acoustic wave (SAW) components, opto-electronic components, hybrid integrated circuits (HICs), and multi

14、-chip modules (MCMs) containing any of these components are to be evaluated according to this standard. The test methods described in this standard may also be used to evaluate components that are shipped as wafers or bare chips. To perform the tests, the components must be assembled into a package

15、similar to that expected in the final application. The package used shall be recorded. 2 Reference document JESD625, Requirements for Handling Electrostatic Discharge-Sensitive (ESDS) Devices. 3 Terms and definitions Charged device model (CDM): A specified circuit characterizing an ESD event that oc

16、curs when a device acquires charge through some triboelectric (frictional) or electrostatic induction processes and then abruptly touches a grounded object or surface. Electrostatic discharge (ESD): A sudden transfer of electrostatic charge between bodies or surfaces at different electrostatic poten

17、tials. NOTE The terms “discharge”, “pulse”, “ESD event” and “CDM stresses” are equivalent for the purposes of this document. Field-induced charging: A charging method using electrostatic induction. JEDEC Standard No. 22-C101F Page 2 Test Method C101F (Revision of Test Method C101E) 4 Circuit schemat

18、ic for the CDM simulator 4.1 The waveforms produced by the simulator shall meet the specifications of 5.1 through 8. 4.2 A schematic for the CDM test circuit is shown in Figure 1. (Other equivalent circuits are allowed if the generated waveform meets the requirements of 5.1 through 8.) A detachable

19、discharge head (see Figure 1), consisting of the pogo probe, radial resistor, top ground plane, semi-rigid coaxial cable, and the support arm, is used to initiate the discharge. The top ground plane shall be a square conductive plate with edge length of 63.5 mm 6.35 mm (2.5 in 0.25 in). The discharg

20、e path includes a 1 ohm resistive current probe of at least 3 GHz bandwidth for waveform monitoring. The cable from the 1 ohm resistor to the oscilloscope should also have a bandwidth of at least 3 GHz. The thickness of the FR-4 dielectric shall be 0.381 mm 0.038 mm (0.015 in 0.0015 in). The dielect

21、ric constant of the dielectric shall be specified at 4.7(5%) at 1 MHz. The charging resistor shown in figure 1 shall be nominally 100 M or greater. Resistor values higher than 100 M may be used, but this may not allow large devices (greater than 25 mm by 25 mm) to fully saturate before being dischar

22、ged by the probe assembly. This effect can be overcome by adding a delay between discharges in the CDM tester programming software. If using a resistor greater than 100 M, it is recommended that the tester or the device itself be characterized to determine if a delay is needed for discharging large

23、devices. A procedure for this large device delay characterization is given in 6.2.1. Figure 1 Field induced CDM simulator 4.3 The Field-Induced Method shall be used to raise the component potential for a subsequent CDM discharge. The component potential is raised by applying the test voltage to the

24、field charging electrode shown in Figure 1. The size of the charging electrode shall be larger than the size of the component and the waveform generated shall meet the requirements in Table 3. The area of the dielectric should be the same as or larger than the charge plate. 100 M CHARGING RESISTORJE

25、DEC Standard No. 22-C101F Page 3 Test Method C101F (Revision of Test Method C101E) 5 Measurement instrumentation 5.1 Waveform verification requires the following instrumentation: a) Oscilloscope with single shot bandwidth of 1 GHz with nominal 50 ohm input impedance and a real time sample rate of 5

26、gigasamples per second. The bandwidth and sampling rate affect the observed waveform. Use of oscilloscopes with differing bandwidth and sampling rate are permitted only if appropriate hardware or software filtering is used to produce a bandwidth and sampling equivalent to that specified here. b) Ohm

27、meter capable of measuring a resistance of 1.0 0.01 ohm. c) A capacitance meter with a resolution of 0.20 pF, a measurement accuracy of 3% and a measurement frequency of at least 1 MHz. d) Standard Test modules - One small and one large with the dimensions listed in Table 2. Table 1 Test modules Dis

28、k Small Large Diameter mm (inches) 8.89 0.127 (0.350 0.005) 25.4 0.127 (1.000 0.005) Thickness mm (inches) 1.27 0.05 (0.050 0.002) 1.27 0.05 (0.050 0.002) Capacitance at 1 MHz 6.8 pF 5% 55 pF 5% 5.2 The disks shall be made of brass plated with nickel or gold/nickel and may optionally have a gold fla

29、sh coating over the nickel. They shall be manufactured to the dimensions specified in Table 1 and shall be verified once before the initial use. NOTE CAUTION shall be exercised during the manufacture of the disks so that they are free from “burrs”. If the perimeter of the disk has “burrs” then arcin

30、g may occur altering the results. 5.3 The standard test modules for the CDM simulator can be cleaned in an ultrasonic bath using isopropanol for about 20 seconds and dried in a moderate air stream to prevent charge leakage during test operation. 5.4 The capacitance of the small and large disks shall

31、 be measured while sitting on the dielectric/charge plate, and shall conform to the values specified in Table 1. JEDEC Standard No. 22-C101F Page 4 Test Method C101F (Revision of Test Method C101E) 6 Simulator waveform verification 6.1 The three levels of CDM simulator verification tests are: CDM Eq

32、uipment Manufacturer Qualification User Verification Routine Verification The tests are described in Table 2. Table 2 Waveform verification tests Routine Verification Manufacturer Qualification and User Verification Record of waveforms required Yes Yes Check (see 7.1) No Yes Tests (see Table 3) #1 #

33、1, #2, #3, #4 6.2 CDM Equipment Manufacturer Qualification - must be done by the CDM equipment manufacturer when the simulator is installed. High-speed instrumentation must be used, including an oscilloscope that meets the requirements in 5.1. All three qualification tests in clause 8 are required,

34、and the test waveforms must be permanently recorded with copies supplied to the user when requested. 6.2.1 Charging Resistor / Charging Delay Characterization Procedure - Using the large test module disk (see Table 1), measure the average of 10 pulses of the peak current magnitude (Ip) using a +500V

35、 plate voltage. Take one set of measurements with the pre- and post- charge delay setting set to 0 ms. Take another set of measurements with the pre-charge delay set at 500 ms. If the Ip is the same for both measurements, a delay does not need to be added to test large devices. If a delay is needed,

36、 500 ms is long enough for most devices. Alternatively, the tester hardware can be modified by adding a lower valued charging resistor and then re-verified with this procedure. The same procedure can be used on a ground pin of a device to determine the optimum amount of delay needed for a specific d

37、evice. 6.3 User Verification - done during initial acceptance testing, whenever the equipment is serviced, and on a regular basis at least once per month. The same tests are done as in the manufacturers qualification. Waveforms must be recorded and stored for comparison with the manufacturers wavefo

38、rms and the weekly verification waveforms. 6.4 Routine Verification - Performed at the beginning of each shift the simulator is used. Only test #1 in clause 8 is required. The user shall observe the waveforms and compare them with the previously recorded waveforms. 6.5 If the waveforms do not meet t

39、he requirement in clause 8, reject any data obtained after the last successful verification. JEDEC Standard No. 22-C101F Page 5 Test Method C101F (Revision of Test Method C101E) 7 Measurement procedure 7.1 With the ohmmeter, verify that the resistance of the current sensing resistors in all discharg

40、e heads to be used is 1 +/- 0.1 ohm and record the value for use in computing the peak current. 7.2 With the capacitance meter, verify that the capacitance (at 1 MHz) of the small and large disks when placed on the dielectric/charge plate meet the requirements in Table 1. 7.3 With the use of the sta

41、ndard modules in 5.1, perform the four tests in clause 8. For each test, 1) Raise the potential of the standard test module to the voltage indicated in Table 3. 2) Discharge the standard test module at least three times at both positive and negative polarities. NOTE With the Field-Induced CDM techni

42、que, both discharge polarities are obtained on alternate discharges with a single power supply setting. Therefore the power supply voltage may be set to either polarity. The peak currents should have the same magnitude but opposite sign for the two discharge polarities. 3) Record the waveforms using

43、 the oscilloscope and take the average values of the parameters specified in Table 3. 4) Repeat the step 1 through step 3 for additional discharge heads as needed. 5) If the waveform characteristics do not meet the requirements in Table 3, clean the test modules (see 6.3) and repeat step 1 through s

44、tep 3. 6) If the waveform still can not meet the requirements in Table 3, any data obtained since the last verification shall be invalidated and the simulator shall be serviced. JEDEC Standard No. 22-C101F Page 6 Test Method C101F (Revision of Test Method C101E) 8 Waveform characteristics The wavefo

45、rms shall appear as shown in Figure 2 for the positive polarity and its reverse for the negative polarity. The average values specified in 7.3 shall meet the specifications in Table 3. Table 3 CDM waveform characteristics Test Number #1 #2 #3 #4 Standard test module Small Small Large Large Test volt

46、age (V) 500 ( 5%) 1000 ( 5%) 200 ( 5%) 500 ( 5%) Peak current magnitude (A) Ip 5.75 ( 15%) 11.5 ( 15%) 4.5 ( 15%) 11.5 ( 15%) Rise time (ps) tr = 100 V and 200 ms) between discharges for the component to reach the full test voltage level. Verify a discharge pulse occurs for each polarity by monitori

47、ng the discharge event detector output or connecting an oscilloscope to the current monitoring resistor. NOTE If there are concerns about the repeatability of current pulses, it is recommended to monitor and record the peak current with an oscilloscope that meets or exceeds the requirements in 5.1.

48、Stresses may be partitioned by polarity, using a sample size of at least three units per polarity. Pins may also be partitioned into one or more sets of samples, provided that each pin of the device is a member of at least one set. Each set should have a minimum of three units. Different devices may

49、 be used for each polarity as long as at least three devices are used for each polarity; i.e., 3 units for positive discharge and 3 units for negative discharge. Separate devices may also be used for different pin groups as long as each group is tested on 3 devices. 10.5 Test each of the components, using the failure criteria in 11. 10.6 Components that pass the test may be reused at other voltage levels. Components that fail may not be used in tests at other levels. It is permitted to use new components for every voltage level. Th