JEDEC JESD22-B118-2011 Semiconductor Wafer and Die Backside External Visual Inspection.pdf

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1、JEDEC STANDARD Semiconductor Wafer and Die Backside External Visual Inspection JESD22-B118 MARCH 2011 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subseq

2、uently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in

3、selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or arti

4、cles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to produ

5、ct specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this stand

6、ard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technol

7、ogy Association 2011 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please

8、refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may

9、 obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 22-B118 Page 1 Test Metho

10、d B118 TEST METHOD B118 SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION (From JEDEC Board Ballot JCB-11-20, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test methods for Packaged Devices.) 1 Scope Semiconductor wafer and die backside external visual insp

11、ection is an examination of the external non-active surface area (hereafter called backside) of processed semiconductor wafers or die. This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external v

12、isual inspection and is a non-invasive and non-destructive examination that can be used for qualification, quality monitoring, and lot acceptance. Alternate methods of inspection or techniques that provide assurance to Clause 6 elements are acceptable (e.g., functional testing, automated inspection

13、equipment, in-line manufacturing operations, etc.). This test method is applicable to: Backside inspection of semiconductor wafers and die. Wafers and die sampled for external visual inspection must be representative of final product. This test method does not apply to or require any inspection, mea

14、surement, or analysis other than the procedure described in clause 5.0. Recommended tools and equipment for this test method are presented in clause 4.0; use of substitute tools or equipment to perform this test method is acceptable provided correlated results are obtained. 2 Terms and definitions a

15、rc: A visual anomaly that is a curved scratch. blemish: A visual anomaly that is an area of inconsistent finish. burn mark: A visual anomaly with a burned appearance. chip out: Damage resulting from a volume of material being removed by mechanical impact. crack (in a wafer or die): A fracture within

16、 the bulk material of a wafer or die. critical area: An area of the wafer or die for which the inspection criteria is more stringent. NOTE The critical area should be stipulated by the appropriate drawing or specification. dice: Plural of “die“. diced wafer: A wafer that has been separated into indi

17、vidual dice. JEDEC Standard No. 22-B118 Page 2 Test Method B118 2 Terms and definitions (contd) die: A separated part of a wafer (or in some cases, a whole wafer) intended to perform a function or functions in a device. die backside: The side of a die that does not contain fabricated semiconductor c

18、ircuits or circuit elements. die lot: A batch of dice manufactured under a given set of conditions. dimple: A visual anomaly that is a shallow dip. ding: A visual anomaly that is an indentation made by mechanical impact. etch mark: A visual anomaly having a discolored or hazy appearance on the wafer

19、 / die that has resulted from etching. film: A thin layer of a substance that has a specified edge or boundary and thickness that ranges from indiscernible to measurable. foreign film: A visual anomaly that is a film not stipulated by design, specification, or applicable product drawings, nor intent

20、ionally introduced by specified processing. foreign material (on or in a wafer or die surface): Any adhering material that is not part of the wafer or die under inspection and cannot be removed by the methods of a dry-gas blow-off, vacuum, and/or by a suitable brush with the methods implementation n

21、ot damaging the surface of the wafer or die. foreign stain: A visual anomaly that is a stain not stipulated by design, specification, or applicable product drawings, nor intentionally introduced by specified processing. haze: A visual anomaly having a partially opaque or cloudy appearance. inspectio

22、n lot: A number of samples from a wafer or die lot that are used for evaluation. known good die: A die that has been processed through test with or without burn-in prior to final assembly to guarantee functionality. native film: An incidental film or a film stipulated by design, present at the wafer

23、 or die level, that was created by specified processing. NOTE The film may exhibit rainbow coloration or other differences in color shading, be spotty or present on localized areas on the wafer or die, or cover a large area. native stain: A visual anomaly, present at the wafer or die level, consisti

24、ng of an incidental stain that was created by specified processing. NOTE The stain may exhibit rainbow coloration or other differences in color shading, be spotty or present on localized areas on the wafer or die, or cover a large area. non-critical area (of a wafer or die): An area of the wafer or

25、die (typically at the edge) for which the inspection criteria are less stringent. JEDEC Standard No. 22-B118 Page 3 Test Method B118 2 Terms and definitions (contd) pit: A visual anomaly that is an indentation. process of record (POR): The specified manufacturing processes with no changes allowed un

26、less proper approval is obtained in accordance with the requirements of JESD46. processed wafer: A wafer that has had an operation or process performed on it to accomplish a particular objective. scratch: A visual anomaly consisting of a line or a series of lines caused by abrasion. scuff: A visual

27、anomaly having a rough appearance caused by abrasion. stain: A visual anomaly consisting of a discolored foreign material area that has a definite edge or boundary but has no measureable thickness. temporary chip attach (TCA): The process used to temporarily join a die to a substrate substrate and t

28、hen to remove the die from the substrate. thinned wafer: A wafer that is reduced in thickness to a specified value. wafer backside: The side of the wafer that does not contain fabricated semiconductor circuits or circuit elements. wafer backside grind: A process of abrading the wafer backside with a

29、 fine grit to eliminate surface scratches or to create a thinned wafer. wafer backside metallization: A metal film layer on the wafer backside surface. wafer lot: A quantity of wafers that are processed together as a batch under a given set of conditions. JEDEC Standard No. 22-B118 Page 4 Test Metho

30、d B118 3 References and / or Other Useful Documents 3.1 IPC1/JEDEC2IPC-T-50, Terms and Definitions for Interconnecting and Packaging Electronic Circuits JESD46, Guidelines for User Notification of Product/Process Changes by Semiconductor Suppliers JESD88, Dictionary of Terms for Solid State Technolo

31、gy JEP120, Index of Terms and Abbreviations Defined in JEDEC Publications JESD625, Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices 3.2 ANSI3ANSI/ESD S20.20, Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive

32、Devices) 3.3 Electrostatic Discharge Association (ESD)4EOS/ESD S8.1, Protection of Electrostatic Discharge Susceptible Items - Symbols - ESD Awareness 4 Apparatus The following is a list of typical tools used to perform the test outlined in this standard. This test method does not preclude the use o

33、f specialized tools or equipment to inspect or measure wafers or die backsides for conformance to physical specifications or other requirements as necessary to meet product acceptance. ESD grounded workstation ESD grounded wrist strap Automated inspection station equipment (if applicable as a substi

34、tute for manual equipment) Microscope or other magnifying aids (capable of appropriate magnification per applicable product drawings and / or specifications) Vacuum pickup or other suitable manual or automatic handling tools Clean room facilities, as appropriate for the item being inspected Antistat

35、ic finger cots Air or nitrogen blow gun Vacuum cleaning tool Brush Surface roughness inspection tool (if required) Appropriate lighting source (if required) 1www.ipc.org 2www.jedec.org 3www.ansi.org 4www.esda.org JEDEC Standard No. 22-B118 Page 5 Test Method B118 5 Procedure Semiconductor wafer and

36、die to be inspected shall be carefully handled and positioned using suitable tools and employing appropriate cleanliness controls. At all times proper ESD handling procedures must be followed. Loose, dry foreign material (FM) may be removed by brush, vacuumed off, or blown off the backside surface u

37、sing clean, dry, filtered air. The semiconductor wafer and die shall be inspected and visual observations verified by using appropriate magnification as defined by application requirements and documented in applicable drawings and /or specifications. Additional lighting may be required to enhance th

38、e inspection. Unusual observations must be evaluated to verify acceptance to Clause 6 inspection elements. The same elements (clause 6) shall apply to both the external visual inspection and to any specialized analyses used for verification. Die and wafer backside inspection requirements are based o

39、n final application conditions. Die (Dice) or wafer(s) that will require additional backside processing (i.e., die marking, direct lid or heatsink placement, etc.) require cleanliness and surface conditions specific for the next processing step. Elements in Clause 6 apply. Use of materials such as a

40、 TCA process to test and/or burn-in die to guarantee functionality may leave residuals on backside surfaces. Wafers and dice processed with these materials must be inspected and meet Clause 6. Alternate methods of inspection or techniques that provide assurance to Clause 6 elements are acceptable (e

41、.g., functional testing, automated inspection equipment, in-line manufacturing operations, etc.). NOTE 1 Typical magnification is from 1X to 45X power for backside inspection. This range doesnt exclude the possibility for higher magnification power when required. NOTE 2 Magnification that is too low

42、 in power will not capture critical defects; magnification that is too high will increase cosmetic defect observations. JEDEC Standard No. 22-B118 Page 6 Test Method B118 6 Inspection elements 6.1 General An example of a reporting form is provided in Annex A. Examples of wafer and die anomalies are

43、presented in Annex B. 6.1.1 Criteria 6.1.1.1 Critical and non-critical areas as defined by an applicable drawing and/or specification should be used for inspection requirements. Criteria may be different between critical and non-critical areas per the applicable drawings and/or specifications. 6.1.1

44、.2 Backside metallization coverage, when required, must be evaluated to assure all requirements are met according to the applicable process drawings and/or specifications 6.1.2 Rejectable when non-compliant 6.1.2.1 Any physical dimension which is non-conforming to an applicable drawing and/or specif

45、ication. 6.1.2.2 Any physical damage that is non-conforming to an applicable drawing and/or specification. This includes, but is not limited to etch marks, pits, scuffs, dimples, dings, and scratches. 6.1.2.3 Any flaw or defect that renders the wafer or die mechanically unfit for use, as defined by

46、an applicable drawing and/or specification. 6.1.2.4 FM that renders the wafer or die mechanically or adhesively unfit for use, as defined by an applicable drawing and / or specification. 6.1.2.5 Any foreign film or stain that is non-conforming to an applicable drawing and/or specification or has not

47、 been evaluated for acceptability. 6.1.2.6 Surface roughness resulting from backside etching, wafer thinning, or other processing is acceptable unless it is not compliant with specific requirements identified on the applicable drawing or specification. 6.2 Semiconductor Wafers 6.2.1 Electrically tes

48、ted wafers When the overall wafer mechanical integrity is assured, selective salvage of good dice from wafers also containing rejected dice is acceptable. 6.3 Semiconductor Dice Die backside defects must meet applicable drawings and/or specification. Characterization of chip outs and/or cracks may b

49、e required to assure requirements are met. Distinction should be made between critical area and non-critical area defect acceptance. JEDEC Standard No. 22-B118 Page 7 Test Method B118 Annex A Report form - External Inspection This form or an equivalent form may be used to report the results of external visual inspection. Part Number Description Lot Number Supplier Applicable Drawing Number Applicable Specification Number Quantity inspected Quantity good Date Inspector Comments - failed condition JEDEC Standard No. 22-B118 Page 8 Test Method B118 Annex