JEDEC JESD2-1982 Digital Bipolar Pinouts for Chip Carriers《片式载体的数字双极逻辑引出端排列》.pdf

《JEDEC JESD2-1982 Digital Bipolar Pinouts for Chip Carriers《片式载体的数字双极逻辑引出端排列》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD2-1982 Digital Bipolar Pinouts for Chip Carriers《片式载体的数字双极逻辑引出端排列》.pdf（11页珍藏版）》请在麦多课文档分享上搜索。

1、. EIA JESD2 82 m 3234600 0005LLb O m T JEDEC- ST.ANDARD -NO. .2 DkGITAL BIPOLAR PINOUTS FOR CHPCARRIERS JEDEC Solid State Products Engineering Council -. (-3 ,.i COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services - EIA JESDZ 62 W 3234600 0005L17 2 W NOTICE This JEDEC S

2、tandard contains material which has been prepared and progres- sively reviewed and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. - JEDEC Standards are designed to serve the public interest through eliminating misunderstandings between man

3、ufacturers and purchasers, facilitating inter- changeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular nee.d. Existence of such standards shall not in any respect preclude any member or non-member of J

4、EDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted

5、 by JEDEC without regard to . whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The inform

6、ation included in JEDEC Standards represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard may be further processed and ultimately become an . EIA

7、Standard. Inquiries, comments, and suggestions relative to the content of this -JEDEC Standard should be addressed to the JEDEC Executive Secretary at the EIA Headquarters. JEDEC Electronic Industries Association 2001 Eye Street N.W. Washington, D.C. 20006 Published by ELECTRONIC INDUSTRIES ASSOCIAT

8、ION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 PRICE: $5.00 Printed in U.S.A. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services! EIA JESD2 82 3234600 0005118 4 - . JEDEC ST,ANDARD NQ. 2 DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS This JEDE

9、C Standard was formulated under the cog- nizance of the JEDEC JC-40.1 Committee on BIPOLAR DIGITAL LOGIC INTEGRATED DEVICES. Note: Numbering of JEDEC Standards follows a numerical sequence which does not necessarily relate to the-publication date of the Dual-in-Line pckage configuration is universal

10、ly accepted and documented in the industrys array of component catalogs. All pin-outs in chip carriers will be by reference to . the de facto Dual-in-Line stancordance . with the appropriate mapping figure, referenced under paragraph 2. When this convention conflicts with the mapping guide- lines in

11、 pdwaph 2 above, this convention will take precedence. The remaining connections then are assigned in sequence leaving the same No connect terminals as indicated in the figures referenced under paragraph 2, .- .J COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services- “ -

12、EIA JESD2 82 m 323YbOO 0005322 b m JEDEC Standard No. 2 Page 3 / (TOP VIEW) CHIP CARRIER TERMINAL NUMBER 0 DUAL IN LINE LEAD NUMBER FIGURE 1: 14 - LEAD PIN-OUT FOR 20 TERMINAL CHIP CARRIER COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD2 82 W 3234b00 0005323

13、 8 W JEDEC Standard No. 2 Page 4 -. 1191 u CHIP CARRIER TERMINAL NUMBER 0 DUAL Ik LINE LEAD NUMBER / FIGURE -2: S. - LEAD PIN-UT .FOR 20 TERMINAL CHIP CARRIER COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Servicesi EIA JESD2 82 m 3234600 0005124 T m JEDEC Standard No. 2 Pa

14、ge 5 /I n 0 CHIP CARRIER TERMINAL NUMBER 0 DUAL IN LINE LEAD NUMBER FIGURE 3: 20 - LEAD PIN-OUT FOR 20-TERMINAL CHIP CARRIER .- c COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD2 82 M 3234600 0005325 3 M JEDEC Standard No. 2 6 (TOP VIEW) 0 CHIP ARRIER - 7. T

15、ERMINAL .NUMBER 0 DUAL IN LINE LEAD NUMBER FIGURE 4: 24 - LEAD PIN-OUT FOR 28 TERMINAL CHIP CARRIER COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD2 82 M 3234600 0005L2b 3 M a JEDEC Standard No. 2 Page .7 c CHIP CARRIER TERMINAL NUMBER 0 DUAL IN LINE LEAD NUMBER FIGURE 5: 28 - LEAD PIN-OUT FOR-28 TERMINAL CHIP CARRIER f W! COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services