ITU-T V 29-1988 9600 BITS PER SECOND MODEM STANDARDIZED FOR USE ON POINT-TO-POINT 4-WIRE LEASED TELEPHONE-TYPE CIRCUITS《点对点四线租用电话型电路上使用的标准化9600bit s调制解调器 -电话网络上的数据交流》.pdf

《ITU-T V 29-1988 9600 BITS PER SECOND MODEM STANDARDIZED FOR USE ON POINT-TO-POINT 4-WIRE LEASED TELEPHONE-TYPE CIRCUITS《点对点四线租用电话型电路上使用的标准化9600bit s调制解调器 -电话网络上的数据交流》.pdf》由会员分享，可在线阅读，更多相关《ITU-T V 29-1988 9600 BITS PER SECOND MODEM STANDARDIZED FOR USE ON POINT-TO-POINT 4-WIRE LEASED TELEPHONE-TYPE CIRCUITS《点对点四线租用电话型电路上使用的标准化9600bit s调制解调器 -电话网络上的数据交流》.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、INTERNATIONAL TELECOMMUNICATION UNION)45G134 6 TELECOMMUNICATIONSTANDARDIZATION SECTOROF ITU$!4!G0G0#/-5.)#!4)/./6%2G0G04(%G0G04%,%0(/.%G0G0.%47/2+G0“)43G0G00%2G0G03%#/.$G0G0-/$%-34!.$!2$):%$G0G0 amended at Geneva, 1980, Malaga-Torremolinos, 1984, and at Melbourne, 1988)1 IntroductionThis modem is i

2、ntended to be used primarily on special quality leased circuits, e.g. Recommendation M.10201 or M.1025 2 circuits but this does not preclude the use of this modem over circuits of lower quality at the discretionof the Administration concerned (see Notes 1 and 2).On leased circuits, considering that

3、there exist and will come into being many modems with features designedto meet the requirements of the Administrations and users, this Recommendation in no way restricts the use of any othermodems.The principal characteristics of this recommended modem for transmitting data at 9600 bits per second o

4、nleased circuits are as follows:a) fallback rates of 7200 and 4800 bits per second;b) capable of operating in a duplex or half-duplex mode with continuous or controlled carrier;c) combined amplitude and phase modulation with synchronous mode of operation;d) inclusion of an automatic adaptive equaliz

5、er;e) optional inclusion of a multiplexer for combining data rates of 7200, 4800 and 2400 bits per second (seeNote 3).Note 1 - The principal use of this recommended modem is on 4-wire leased circuits. Other applications, such asstand-by operation on the switched network, should be points for further

6、 study.The types of special quality circuits, e.g. M.1020 1 or M.1025 2 should be studied.Note 2 - The values of some circuit characteristics, for example, noise and nonlinear distortion, are subject tofurther study.Note 3 - When the multiplexer option is installed, provisions in 12 may supersede pr

7、ovisions given in othersections.Note 4 - Attention should be given to the selection of appropriate equalization techniques in the modemimplementation, if acceptable performance on circuits conforming to Recommendation M.1025 is desired.2 Line signals2.1 The carrier frequency is to be 1700 1 Hz. No s

8、eparate pilot frequencies are provided. The power levels usedwill conform to Recommendation V.2.2.2 Signal space coding2.2.1 At 9600 bits per second, the scrambled data stream to be transmitted is divided into groups of four consecutivedata bits (quadbits). The first bit (Q1) in time of each quadbit

9、 is used to determine the signal element amplitude to betransmitted. The second (Q2), third (Q3) and fourth (Q4) bits are encoded as a phase change relative to the phase of theimmediately preceding element (see Table 1/V.29). The phase encoding is identical to Recommendation V.27.The relative amplit

10、ude of the transmitted signal element is determined by the first bit (Q1) of the quadbit andthe absolute phase of the signal element (see Table 2/V.29). The absolute phase is initially established by thesynchronizing signal as explained in 8 below.2 Fascicle VIII.1 - Rec. V.29Figure 1/V.29 shows the

11、 absolute phase diagram of transmitted signal elements at 9600 bits per second.At the receiver the quadbits are decoded and the data bits are reassembled in correct order.2.2.2 At the fallback rate of 7200 bits per second, the scrambled data stream to be transmitted is divided into groupsof three co

12、nsecutive data bits. The first data bit in time determines Q2 of the modulator quadbit. The second and thirddata bits determine Q3 and Q4 respectively of the modulator quadbit. Q1 of the modulator quadbit is a data ZERO foreach signal element. Signal elements are determined in accordance with 2.2.1

13、above. Figure 2/V.29 shows the absolutephase diagram of the transmitted signal elements at 7200 bits per second.2.2.3 At the fallback rate of 4800 bits per second (see Table 3/V.29), the scrambled data stream to be transmitted isdivided into groups of two consecutive data bits. The first data bit in

14、 time determines Q2 of the modulator quadbit andthe second data bit determines Q3 of the modulator quadbit. Q1 of the modulator quadbit is a data ZERO for each signalelement. Q4 is determined by inverting the modulo 2 sum of Q2 + Q3. The signal element is then determined inaccordance with 2.2.1 abov

15、e. Figure 3/V.29 shows the absolute phase diagram of transmitted signal elements at 4800bits per second.The phase changes are identical with Recommendation V.26 (alternative A) and the amplitude is constant witha relative value of 3.TABLE 1/V.29Q2 Q3 Q4 Phase change (see Note)00001111001111001001100

16、104590135180225270315Note - The phase change is the actual on-line phase shift in thetransition region from the centre of one signalling element to thecentre of the following signalling element.Fascicle VIII.1 - Rec. V.29 3TABLE 2/V.29Absolute phase Q1 Relative signal elementamplitude0, 90, 180, 270

17、 0 31545, 135, 225, 315 02132FIGURE 1/V.29Signal space diagram at 9600 bit/sFIGURE 2/V.29Signal space diagram at 7200 bit/s4 Fascicle VIII.1 - Rec. V.29TABLE 3/V.29Data bits Quadbits Phase changeQ1 Q2 Q3 Q4001101100000001101101010090180270FIGURE 3/V.29Signal space diagram at 4800 bit/s3 Data signall

18、ing and modulation ratesThe data signalling rates shall be 9600, 7200 and 4800 bits per second 0.01%. The modulation rate is2400 bauds 0.01%.4 Received signal frequency toleranceThe carrier frequency tolerance allowance at the transmitter is 1 Hz. Assuming a maximum frequency drift of 6 Hz in the co

19、nnection between the modems, then the receiver must be able to accept errors of at least 7 Hz in thereceived signal frequency.5 Interchange circuitsFascicle VIII.1 - Rec. V.29 55.1 List of interchange circuits (Table 4/V.29)TABLE 4/V.29Interchange circuit (see Note 1)No. Designation102103104105(see

20、Note 2)106107109111(see Note 3)113114115140( see Note 4)141(see Note 4)142Signal ground or common returnTransmitted dataReceived dataRequest to sendReady for sendingData set readyData channel received line signal detectorData signalling rate selector (DTE source)Transmitter signal element timing (DT

21、E source)Transmitter signal element timing (DTE source)Receiver signal element timing (DCE source)Loopback/Maintenance testLocal loopbackTest indicatorNote 1 - All essential interchange circuits and any others which are provided shall comply with the functional andoperational requirements of Recomme

22、ndation V.24. All interchange circuits provided shall be properly terminated inthe data terminal equipment and in the data circuit-terminating equipment in accordance with the appropriateRecommendation for electrical characteristics (see 6).Note 2 - Not essential for continuous carrier operation.Not

23、e 3 - A manual selector shall be implemented which determines the two data signalling rates selected by circuit111. The manual selector positions shall be designated 9600/7200, 9600/4800 and 7200/4800. The ON condition ofcircuit 111 selects the higher data signalling rate and the OFF condition of ci

24、rcuit 111 selects the lower data signallingrate.Note 4 - Interchange circuits 140 and 141 are optional.5.2 Threshold and response times of circuit 1095.2.1 Threshold- greater than - 26 dBm: circuit 109 ON;- less than -31 dBm: circuit 109 OFF.The condition of circuit 109 for levels between -26 dBm an

25、d -31 dBm is not specified except that the signaldetector shall exhibit a hysteresis action, such that the level at which the OFF to ON transition occurs is at least 2 dBgreater than that for the ON to OFF transition.6 Fascicle VIII.1 - Rec. V.295.2.2 Response times- ON to OFF: 30 9 ms;- OFF to ON:1

26、) for initial equalization, circuit 109 must be ON prior to user data appearing on circuit 104;2) for re-equalization during data transfer, circuit 109 will be maintained in the ON condition; during thisperiod, circuit 104 may be clamped to the binary 1 condition;3) after a line signal interruption

27、that lasts more than the ON to OFF response time:a) when no new equalization is needed, 15 10 ms,b) when a new equalization is needed, circuit 109 must be ON prior to user data appearing oncircuit 104.Response times of circuit 109 are the times that elapse between the connection or removal of a line

28、 signal to orfrom the modem receive line terminals and the appearance of the corresponding ON or OFF condition on circuit 109.Note - Circuit 109 ON to OFF response time should be suitably chosen within the specified limits to ensure thatall valid data bits have appeared on circuit 104.5.3 Response t

29、ime for circuit 106The time between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit 106 shall beoptionally 15 ms 5 ms or 253.5 ms 0.5 ms.The short delay is used when circuit 105 does not control the transmitter carrier. The long delay is used whencircuit 105 controls

30、transmitter carrier and a synchronizing signal is initiated by the OFF to ON transition of circuit 105.The time between the ON to OFF transition of circuit 105 and the ON to OFF transition of circuit 106 shall besuitably chosen to ensure that all valid signal elements have been transmitted.5.4 Fault

31、 condition of interchange circuits(See Recommendations V.28, 7 for association of the receiver failure detection types.)5.4.1 The DTE should interpret a fault condition on circuit 107 as an OFF condition using failure detection type 1.5.4.2 The DCE should interpret a fault condition on circuits 105

32、and 108 as an OFF condition using failure detectiontype 1.5.4.3 All other circuits not referred to above may use failure detection type 0 or 1.6 Electrical characteristics of interchange circuitsUse of electrical characteristics conforming to Recommendation V.28 is recommended together with theconne

33、ctor pin assignment plan specified by ISO 2110.Note - Manufacturers may wish to note that the long-term objective is to replace electrical characteristicsspecified in Recommendation V.28, and that Study Group XVII has agreed that the work shall proceed to develop amore efficient, all balanced, inter

34、face for the V-Series application which minimizes the number of interchange circuits.7 Timing arrangementsClocks should be included in the modem to provide the data terminal equipment with transmitter signal elementtiming, circuit 114, and receiver signal element timing, circuit 115. In this arrange

35、ment, the transmitter may either run asFascicle VIII.1 - Rec. V.29 7an independent timing source or with loopback timing (transmit timing slaved to receive timing). Loopback timing maybe desirable in some network applications. Alternatively, the transmitter signal element timing may be originated in

36、 thedata terminal equipment and be transferred to the modem via interchange circuit 113.8 Synchronizing signalsTransmission of synchronizing signals may be initiated by the modem or by the associated data terminalequipment. When circuit 105 is used to control the transmitter carrier the synchronizin

37、g signals are generated during theinterval between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit 106. When thereceiving modem detects a circuit condition which requires resynchronizing, it shall turn circuit 106 OFF and generate asynchronizing signal.The synchronizi

38、ng signals for all data signalling rates are divided into four segments as in Table 5/V.29.TABLE 5/V.29Segment 1 Segment 2 Segment 3 Segment 4Total ofSegments1, 2, 3 and 4Type of line signal No transmittedenergyAlternations EqualizerconditioningpatternScrambled allbinary ONEsTotalsynchronizingsignal

39、Number of symbolintervals48 128 384 48 608Approximate timein msa)20 53 160 20 253a)Approximate times are provided for information only. The segment duration is determined by the exact number of symbol intervals.8.1 Segment 2 of the synchronizing signal consists of alterations between two signal elem

40、ents. The first signalelement (A) transmitted has a relative amplitude of 3 and defines the absolute phase reference of 180. The secondsignal element (B) transmitted depends on the data signalling rate. Figure 4/V.29 shows the B signal element at each ofthe data signalling rates. Segment 2 alternate

41、s ABAB.ABAB for 128 symbol intervals.FIGURE 4/V.29Signal space diagram showing synchronizing signal points8 Fascicle VIII.1 - Rec. V.298.2 Segment 3 of the synchronizing signals transmits two signal elements according to an equalizer conditionpattern. The first signal element (C) has a relative ampl

42、itude of 3 and absolute phase of 0. The second signal element(D) transmitted depends on the data signalling rate. Figure 4/V.29 shows the D signal element at each of the datasignalling rates. The equalizer conditioning pattern is a pseudo-random sequence generated by the polynomial:1 + x-6+ x-7Each

43、time the pseudo-random sequence contains a ZERO, point C is transmitted. Each time the pseudo-randomsequence contains a ONE, the point D is transmitted. Segment 3 begins with the sequence CDCDCDC according tothe pseudo-random sequence and continues for 384 symbol intervals. The detailed pseudo-rando

44、m sequence generationis described in Appendix I.8.3 Segment 4 commences transmission according to the encoding described in 2.2 above with continuousbinary ONEs applied to the input of the data scrambler. Segment 4 duration is 48 symbol intervals. At the end ofSegment 4, circuit 106 is turned ON and

45、 user data are applied to the input of the data scrambler.9 ScramblerA self-synchronizing scrambler/descrambler having the generating polynomial 1 + x-18+ x-23, shall be includedin the modem.At the transmitter the scrambler shall effectively divide the message polynomial, of which the input datasequ

46、ence represents the coefficients in descending order, by the scrambler generating polynomial to generate thetransmitted sequence. At the receiver the received polynomial, of which the received data sequence represents thecoefficients in descending order, shall be multiplied by the scrambler generati

47、ng polynomial to recover the messagesequence.The detailed scrambling and descrambling processes are described in Appendix II.10 EqualizerAn automatic adaptive equalizer shall be provided in the receiver.The receiver shall incorporate a means of detecting loss of equalization and initiating a synchro

48、nizing signalsequence in its associated local transmitter.The receiver shall incorporate a means of detecting a synchronizing signal sequence from the remote transmitterand initiating a synchronizing signal sequence in its associated local transmitter, which may be initiated at any timeduring the re

49、ception of the synchronizing signal sequence, regardless of the state of circuit 105.Either modem can initiate the synchronizing signal sequence. The synchronizing signal is initiated when thereceiver has detected a loss of equalization or when circuit 105 OFF to ON transition occurs in the carrier controlledmode, as described in 5.3 above. Having initiated a synchronizing signal, the modem expects a synchronizing signalfrom the remote transmitter.If the modem does not receive a synchronizing signal from the remote transmitter