ITU-T V 28-1993 Electrical Characteristics for Unbalanced Double-Current Interchange Circuits (Study Group XVII)《非平衡双流接口电路的电特性》.pdf

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1、ITU-T RECMN*V-28 (REV* +3 volts 1 O OFF ON 6 Signal characteristics The following limitations to the characteristics of signals transmitted across the interchange point, exclusive of external interference, shall be met at the interchange point when the interchange circuit is loaded with any receivin

2、g circuit which meets the characteristics specified in clause 3. These limitations apply to all (data, control and timing) interchange signals unless otherwise specifkd. 1) Au interchange signals entering into the transition region shall proceed through this region to the opposite signal state and s

3、hall not re-enter this region until the next significant change of signal condition, except as indicated in ) below. 2) There shall be no reversal of the direction of voltage change while the signal is in the transition region, except as indicated in 6) below. 3) For control interchange circuits, th

4、e time required for the signal to pass through the transition region during a change in state shall not exceed one millisecond. For data and timing interchange circuits, the he required for the signal to pass through the transition region during a change in state shall not exceed 1 millisecond or 3%

5、 of the nominal element period on the interchange circuit, whichever is the less. 4) 4 Recommendation V.28 (03/93) 5 To reduce crosstalk between interchange circuits the maximum instantaneous rate of voltage change will be limited. A provisional limit will be 30 volts per microsecond. 6) When electr

6、omechanical devices are used on interchange circuits, points ) and 2) above do not apply to data interchange circuits. 7 Certain applications require detection of various fault conditions in the interchange circuits, e.g.: Detection of generator power-off or circuit failure 1) generator power-off co

7、ndition; 2) 3) open-circuited interconnecting cable; 4) short-circuited interconnecting cable. receiver not interconnected with a generator; The power-off impedance of the generator side of these circuits shall not be less than 300 ohms when measured with an applied voltage (either positive or negat

8、ive polarity) not greater than 2 volts in magnitude referenced to signal ground or common return. The interpretation of a fault condition by a receiver (or load) is application dependent. Each application may use a combination of the following classification: Type O: No interpretation. A receiver or

9、 load does not have detection capability. Type 1: Data circuits assume a binary 1 state. Control and timing circuits assume an OFF condition. The association of the circuit failure detection to particular interchauge circuits in accordance with the above types is a matter of the functional and proce

10、dural characteristics specification of the interface. The interchange circuits monitoring circuit fault conditions in the general telephone network interfaces are indicated in Recommendation V.24. Annex A Operation from 20 kbit/s to 64 kbit/s (This annex forms an integrai part of this Recommendation

11、) Note -It should be noted that actual hardware for V.28 generators and receivers is not designed with a view to operating at signalling rates beyond 20 kbis, and may not meet ali requirements contained in this Recommendation when operated at such signalling rates. Furthermore, the performance of su

12、ch hardware may not meet the requirements of International Standards on signal quality (viz: IS0 7480 and IS0 9543). The oniy application presently recognized by the CCm, where there may be a need to apply V.28 electrical characteristics at signalling rates higher than 20 kbis is with existing DTEs

13、which are connected to DCEs comprising a data compression capability according to Recommendation V.42 bis. A.l Option1 Limit the load capacitance (CI) on each circuit to the value: Cl m.(pF) 3 c(2500 + Co)20/BR1 - CO L J BR being the maximum bit rate (in kbit/s) considered for the interface and CO t

14、he capacitance associated with the generator side of the interface. Such a limitation of the load capacitance allows to maintain compliance with the 3% of a Unit Interval 0 maximum transition region crossing time requirement of 6.4. Recommendation V.28 (03/93) 5 Ad Option2 Replace, beyond 20 kbits,

15、the 3% requirement of 6.4 by a constant value of 1.5 p. This allows keeping the 2500 pF maximum Cl load capacitance specified in clause 4 at the cost of a transition region crossing relative time increasing from 3% of a UI at 20 kbits up to 9.6% of a UI at 64 kbits. NOTE - Option 1 may be inapplicab

16、le if Co is not smaii relative to 2500 pF (e.g. in the case of a DTE with a long interconnecting cable). Option 2 reduces the operating margins at the interface by adding up to 2% of jitter at 64 kbi/s on the data signals and, for synchronous interfaces, by increasing the timing displacement between

17、 circuits with contradirectional timing relationship (typically up to 15% at 64kbi/s, which may correspond to a sampling error of 30% if there is no phase shift compensation in the data receiver). The added jitter may prevent a DTE operating in start-stop mode at (or near) the 64 kbits limit from co

18、mplying with a category II level of signal quality, as defined by IS0 in standard IS0 7480 (Start-stop Transmission Signal Quality at DTEDCE Interfaces). The added timing displacement may prevent a DTE operating in synchronous mode at (or near) the 64 kbits limit from complying with the requirements of the standard IS0 9543 (Synchronous Transmission Signal Quaiity at DTE/DCE Interfaces) for contradirectionai timing. 6 Recommendation V.28 (03193)