GEIA EIA-IS-103-A-1996 Library of Parameterized Modules (LPM) Version 2 1 0《参数化单元的图书馆 版本210》.pdf

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1、3234bDD Ob77233 DUB EIA-IS/103-A October 1996 edif Electronic Design Interchange Format A DIVISION OF ELECTRONIC INDUSTRIES ASSOCIATION Library of Parameterized Modules Version 2 1 O Copyright Government Electronics for the compare primitive it is the assumed representation of the input (unsigned or

2、 signed). The LPM standard specifies what values are valid for ail recognized properties. Any non-standard value for a standard property is considered an error. 2.2. i. 1 Legal Values for WM-“T Property The only exception to the above is the LPM-“T property. This optional property, which is attached

3、 to instances of cell use, contains additional technology-specific information for use by the silicon vendor tools. There are no standard values for this field and it is there for the design tool vendors and the silicon tool vendors to utilize as needed. This property can always be ignored and the c

4、orrect logic will be constructed, although the logic may not be constructed in the most efficient way. 2.2.2 Universal Properties Some properties apply to all LPM modules. Some of these properties are optional and some are required. Although these properties can be used with any module, they are not

5、 described as one of the required or optional properties in the individual module descriptions. 2.2.2.1 Signal Polarities one bit for binary and four bits for hexadecimal. Examples: “-B- 1 1 1 1 “ - “B 1 1 1 1-“ “HEAD-“ “-HE-“ The “dont cares“ can take on any value for simulation. That is: undefined

6、, one or zero. The regular expressions for string values with dont cares in LPM: “-+?B-O1 A*“ “-+I? H -0-9 a-f A- F-*“ 2-5 Copyright Government Electronics the path must be routed through each storage element (or some of them, anyway) with no intervening logic. The scan testing strategy proceeds as

7、follows: 1. Disable system.clwks (this includes any asynchronous sets or resets). 2. Apply the external test pattern on the Scan-In port and scan (shift) the test pattern in via the externally generated test clock (this clock can use the same wires as the system 3- 1 Copyright Government Electronics

8、 ?x7 = C7 & B7 & At71 4-7 Copyright Government Electronics & Information Technology Association Reproduced by IHS under license with GEIA Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-= 323Lib00 Ob7723b 488 = LPM21O DescriDtion of LPM modules Port Name I Type 4.2

9、.4 LPM-OR Usage omments . Data I Result O Required Data input Requiredpesult of OR operators Vector, LPM-Size times LPM-Width wide Vector, LPM-Width wide * Property Usage LPM-Width Required D- Value Comments LPM Value O Width of output vector. Number of OR gates. D Required LPM Value O I LpM-size I

10、I OR Number of inputs to each OR gate. Number of input buses. Ir tesulb tesulti 4.2.4.3 Where i 4-8 Copyright Government Electronics & Information Technology Association Reproduced by IHS under license with GEIA Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-W 323

11、4b00 Ub79237 314 m Description of LPM modules LPM21O 4.2.4.4 Example Suppose the designers have three 8-bit buses and they want to OR the corresponding bits of the three buses. This is done using an LPM-OR with an LPM-Width of 8 and an LPM-Size of three. The LPM-Width of eight indicates that there a

12、re eight OR gates, and the LPM-Size of three indicates that each OR gate has three inputs. LPM-EPE = LPM-OR LPM-Width = 8 LPM-Size = 3 This diagram is for illustrarive purposes only and is not intended fo speczfi any impiemenrotion details. The function performed by the LPM-OR gate in this case is:

13、OutO = Resulto = Dataut0 I Datalx0 I Dataox0 = AO I BtO I CO Outl = Result, = Dataut1 1 Datalxi Out2 = Result2 = Dataut2 I Datalx2 Out3 = Result3 = DataZx3 I Datalx3 Out4 = Result4 = Datax4 I Datalx4 Dataoxi = A1 I B1 Dataox2 = A2 i B2 Dataox3 = At31 I B3 Dataax4 = A4 Out5 = Results = Datazs I Datal

14、x5 I Dataox5 = A5 Out6 = Result6 = Dataut6 I Datalx6 1 Dataox6 = At61 Out7 = Result7 = Data7 I Datalx7 I Dataox7 = At71 4-9 Copyright Government Electronics & Information Technology Association Reproduced by IHS under license with GEIA Not for ResaleNo reproduction or networking permitted without li

15、cense from IHS-,-,-E 3234b b79238 250 E LPM210 Description of LPM modules Port Name Type Data I Result O . Usage bescription Comments Required Data input Required Result of XOR operators Vector, LPM-Size times LPM-Width wide Vector, LPM-Width wide . Property LPM-Width LPM-Size D Usage Value Comments

16、 Required LPM Value O Width of output vector. Number of XR gates. Required LPM Value O Number of inputs to each XOR gate. Number of input buses. D XOR 3 Tesulto O I Width of input and output vectors 4-12 Copyright Government Electronics & Information Technology Association Reproduced by IHS under license with GEIA Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-