EN 62416-2010 en Semiconductor devices - Hot carrier test on MOS transistors《半导体器件 MOS晶体管的热载子试验》.pdf

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1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationSemiconductor devices Hot carrier test on MOS transistorsBS EN 62416:2010National forewordThis British Standard is the UK implementation of EN 62416:2010. It is identical to IEC

2、62416:2010.The UK participation in its preparation was entrusted to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users

3、 are responsible for its correct application. BSI 2010ISBN 978 0 580 58621 7ICS 31.080.30Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 31 July 2010.Amendments is

4、sued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 62416:2010EUROPEAN STANDARD EN 62416 NORME EUROPENNE EUROPISCHE NORM June 2010 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnisc

5、he Normung Management Centre: Avenue Marnix 17, B - 1000 Brussels 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 62416:2010 E ICS 31.080 English version Semiconductor devices - Hot carrier test on MOS transistors (IEC 62416:

6、2010) Dispositifs semi-conducteurs - Essai de porteur chaud sur les transistors MOS (CEI 62416:2010) Halbleiterbauelemente - Hot-Carrier-Prfverfahren fr MOS-Transistoren (IEC 62416:2010) This European Standard was approved by CENELEC on 2010-06-01. CENELEC members are bound to comply with the CEN/CE

7、NELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any

8、 CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official vers

9、ions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal

10、, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. BS EN 62416:2010EN 62416:2010 - 2 - Foreword The text of document 47/2041/FDIS, future edition 1 of IEC 62416, prepared by IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approv

11、ed by CENELEC as EN 62416 on 2010-06-01. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent rights. The following dates were fixed: latest date by w

12、hich the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2011-03-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2013-06-01 _ Endorsement notice The text of the International Standar

13、d IEC 62416:2010 was approved by CENELEC as a European Standard without any modification. _ BS EN 62416:2010 2 62416 IEC:2010 CONTENTS 1 Scope.5 2 Abbreviations and letter symbols 5 3 Test structures .6 4 Stress time .6 5 Stress conditions6 6 Sample size7 7 Temperature.7 8 Failure criteria 7 9 Lifet

14、ime estimation method.7 9.1 DC acceleration models 7 9.1.1 General .7 9.1.2 Method 1: extrapolation vs. drain currrent8 9.1.3 Method 2: extrapolation vs. drain bias and channel length .8 9.2 AC estimation model .9 10 Lifetime requirements .9 11 Reporting .9 Bibliography10 BS EN 62416:201062416 IEC:2

15、010 5 SEMICONDUCTOR DEVICES HOT CARRIER TEST ON MOS TRANSISTORS 1 Scope This standard describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime. 2 Abbrev

16、iations and letter symbols In this document the following abbreviations and letter symbols apply: MOS Metal Oxide Semiconductor NMOS n-channel MOS transistor PMOS p-channel MOS transistor (C)MOS Complementary MOS L m length of polysilicon gate of MOS transistor W m width of polysilicon gate of MOS t

17、ransistor Lnominalm minimum L allowed by the design rules of the process Wnominalm minimum W allowed by the design rules of the process VgsV gate-source voltage of MOS transistor VdsV drain-source voltage of MOS transistor VbsV backgate-source voltage of MOS transistor IdsA: drain-source current of

18、MOS transistor IbA substrate current of MOS transistor IgnA gate current of MOS transistor Vgs,stressV Vgsbiasing condition during hot carrier stress Vds,stressV Vdsbiasing condition during hot carrier stress Vds,use_maxV maximum Vdsallowed by the design rules of the process as stated in the design

19、manual Vds,breakdownV Vdsat which avalanche or punch-through currents become dominant; defined as Vdsat which Ids= 1,5 (Idsat Vds,use_max) while Vgs= Vds,use_maxVtV threshold voltage of MOS transistor defined as Vgsvoltage at which Ids= 0,01 W / L A. Other (commonly agreed) definitions of Vtare also

20、 allowed as long as this is clearly reported. gmA/V transconductance of MOS transistor gm,maxA/V maximum transconductance of MOS transistor Ids,sat A saturated drain-source current at Vgs= Vds= Vds,use_,max; Ids,sat_forwardmeasured with source and drain having same polarity as during stress, Ids,sat

21、_reversemeasured with source and drain polarity interchanged with respect to stress. L( MOST) length of the square MOS transistor (L = W) gm,max( MOST) gm,maxof the square MOS transistor (L = W) BS EN 62416:2010 6 62416 IEC:2010 s lifetime of the MOS transistor Leffm effective electrical channel len

22、gth of MOS transistor; the Lefffor a given L is determined using the gm,maxof a large square ( ) MOS transistor with W = L Lnominal. 3 Test structures For the evaluation of the hot carrier degradation vulnerability of a technology, nominal transistors (L = Lnominal) are recommended. The following ga

23、te lengths are recommended when lifetime extrapolation versus L is needed (see 9.1): L = 1,0 Lnominal, L = 1,5 Lnominal, L = 2,0 Lnominal, L = 5,0 Lnominal, L = W. Gates and sources of the transistors may be combined to reduce the number of bond pads required for these test structures. Typical value

24、s for W are 10 m for Lnominal 1 m, and 20 m for Lnominal1m. A transistor with small W (e.g. W = Lnominal) can be used to evaluate the occurrence of potential narrow width effects. The nominal transistor shall be placed with various orientations on the wafer (e.g. one with the orientation of its gate

25、 parallel to the flat of the wafer and one with its gate orientation perpendicular to the flat) whenever asymmetry effects due to ion implantation are expected. 4 Stress time Typically 40 000 s (one night), in some low voltage cases 200 000 s (1 weekend); readpoints logarithmically spaced (at least

26、3 per decade). Stress times shall be chosen such that the degradation exceeds at least 20 % of the maximum value for the selected failure criterion (see Clause 8). 5 Stress conditions At least 3 different Vds,stressconditions where Vds,stress_max Vds,breakdown, Vbs = 0 V. NMOS transistors are stress

27、ed at maximum substrate current conditions. Usually, the maximum substrate current occurs at approximately Vgs,stress = Vds,stress/ 2 V 0,5 V (1) If this is not the case for a certain technology, one shall determine the appropriate Vgs,stressby substrate current measurements. For deep-submicron tran

28、sistors worst-case degradation may not occur at maximum substrate current, and it is therefore recommended that the worst-case stress conditions are checked. PMOS transistors are stressed at maximum gate current conditions. Usually, maximum gate current occurs at approximately Vgs,stress= Vt 1,0 V (

29、2) (e.g. Vt = 0,8 V then Vgs= 1,8 V) If this is not the case for a certain technology, one shall determine the appropriate Vgs,stressby gate current measurements. BS EN 62416:201062416 IEC:2010 7 For accurate determination of the life time it is recommended to reach the failure criterion during the

30、stress. This can be achieved by choosing a high Vdsvalue. A reasonable starting value is Vds= 0,9 Vds,breakdown. If this is not feasible it is recommended to take at least two time decades of valid data and extrapolate to the failure criterion. 6 Sample size The sample size is not prescribed. Too lo

31、w sample sizes will result in short life times due to the 60 % confidence requirement for extrapolation. It is recommended to use at least 3 Vdsbias conditions and 4 different W/L ratios. The resulting number of datapoints is for example 3 (Vds) 4 (transistors) 2 batches = 24 datapoints. 7 Temperatu

32、re Room temperature, kept constant within 3 C. 8 Failure criteria Failure criteria have to be selected for one or more of the following parameters: gm,max, Vt, Ids,sat_ forward, Ids,sat_reverse, Ids,lin. Recommended criteria are given below: |gm,max/gm,max| = 10% at Vds= 0,1 V or |Vt| = 0,02xVdd,max

33、with a minimum value of 100 mV at Vds= 0,1 V or |Ids,sat/Ids,sat|forward = 10 % or |Ids,sat/Ids,sat|reverse = 10 % or |Ids,lin/Ids,lin|forward = 10 % NMOS transistors typically show a decrease in gmand Ids,satand an increase in |Vt|. PMOS transistors typically show an increase in gmand Ids,satand a

34、decrease in |Vt|. Lifetimes can be determined by interpolation and extrapolation of data. However it is recommended to disregard data where the shift in gm, Ids,sator Vtdid not exceed 20 % of the failure criteria or when the data must be extrapolated by more than one decade in time in order to reach

35、 the failure criteria. 9 Lifetime estimation method 9.1 DC acceleration models 9.1.1 General Two different methods for lifetime estimation are given. Method 1 uses the dependence of lifetime on the drain current, and requires only the nominal transistor. Method 2 uses the dependency of lifetime on g

36、ate length, and requires test structures with different L. Method 2 is used when the dependency of lifetime on channel length is needed. BS EN 62416:2010 8 62416 IEC:2010 9.1.2 Method 1: extrapolation vs. drain current For NMOS transistors, extrapolation is done according to = A (Ib)m(3) where A is

37、a process-dependent constant, and m is the substrate current acceleration exponent. For L 0,5 m, a better fit may be obtained with 11: *Ids= A (Ib/Ids)m(4) For PMOS transistors, extrapolation is done according to 2: = A (Ig)m(5) The parameters A and m are found by plotting log() versus log(Ib) or lo

38、g(Ig) (see equation 4 and equation 6 respectively), or by plotting log(*Id) versus log(Ib/Id) (see equation 5). A straight line is found with slope m and intercept log(A). 9.1.3 Method 2: extrapolation versus drain bias and channel length For NMOS transistors, the Takeda model 3 can be used for the

39、channel length dependence. = A exp(B / Vds,stress) (Leff)C(6) where A is a process-dependent constant; B is the process-dependent voltage acceleration constant; C is the process-dependent channel length acceleration constant. Leffis given by Leff= L( MOST) gm,max( MOST) / gm,max(L) (7) For PMOS tran

40、sistors, the Woltjer model 4 can be used for the channel length dependence. = A exp(B / Vds,stress) exp(C (Leff) (8) The parameters A, B and C are found from a simultaneous fit of the lifetime as a function of Vds,stress and Leff. For deep submicron CMOS technologies other extrapolation models are a

41、lso used for the channel length dependence of lifetime for both NMOS en PMOS transistors, e.g. = A exp(CxLeff) or = A exp(C/Leff) NOTE In these models, only lifetime data based on one failure criterion should be used at a time. _ 1The figures in square brackets refer to the Bibliography. BS EN 62416

42、:201062416 IEC:2010 9 9.2 AC estimation model For AC applications, lifetime is calculated according to AC= DC tcycle/(trise+tfall) (9) where ACis the lifetime of the AC bias condition, DCthe lifetime of the DC bias condition, tcycleis the cycle time of the AC stress, triseis the rise time of the AC

43、stress, and tfallis the fall time of the AC stress. AC tests are recommended. 10 Lifetime requirements In analog circuits, the required lifetime may be achieved by increasing the minimum Leffallowed in analog designs. Hot carrier lifetime of digital circuitry exceeds the static transistor lifetime b

44、y far due to duty cycle effects and limited sensitivity of digital circuitry to transistor degradation 5. 11 Reporting The following items shall be reported as a minimum, when presenting hot carrier data: number of transistors used as well as their dimensions; stress voltages used; failure criterion

45、 which is reached first; values of the constants A, B and C as well as their sigmas; a plot of the lifetime as a function of 1/Vdsfor all transistors used. BS EN 62416:2010 10 62416 IEC:2010 Bibliography 1 “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, C. Hu, et al, IEEE

46、Transactions on Electron Devices, Vol. ED-32, No. 2, pp. 375-385, 1985 2 “Hot-carrier current modeling and device degradation in surface channel p-MOSFETs”, T-C. Ong, et al., IEEE Transactions on Electron Devices, p. 1658, 1990. 3 “Hot carrier effects in scaled MOS devices”, E. Takeda, Microelectron

47、ics and Reliability, Vol.33, pp. 1687-1711, (1993) 4 “Time dependence of p-MOSFET hot carrier degradation measured and interpreted consistently over ten orders of magnitude”, R. Woltjer, A. Hamada, E. Takeda, IEEE Transactions on Electron Devices, Vol.40, pp. 392-401, (1993) 5 “Relation between the

48、hot carrier lifetime of transistors and CMOS SRAM products”, J.A. van der Pol, J.J. Koomen, 28th Proceedings IRPS, pp. 178-185, (1990) _ BS EN 62416:2010This page deliberately left blankThis page deliberately left blankBSI is the independent national body responsible for preparing British Standardsa

49、nd other standards-related publications, information and services. It presents the UK view on standards in Europe and at the international level. It is incorporated by Royal Charter.British Standards Institution (BSI)raising standards worldwideBSI Group Headquarters389 Chiswick High Road London W4 4A