EN 61188-1-2-1998 en Printed Boards and Printed Board Assemblies - Design and Use Part 1-2 Generic Requirements - Controlled Impedance《印制板和印制板组件 设计和使用 第1-2部分 一般要求 受控阻抗　IEC 61188-1-.pdf

《EN 61188-1-2-1998 en Printed Boards and Printed Board Assemblies - Design and Use Part 1-2 Generic Requirements - Controlled Impedance《印制板和印制板组件 设计和使用 第1-2部分 一般要求 受控阻抗　IEC 61188-1-.pdf》由会员分享，可在线阅读，更多相关《EN 61188-1-2-1998 en Printed Boards and Printed Board Assemblies - Design and Use Part 1-2 Generic Requirements - Controlled Impedance《印制板和印制板组件 设计和使用 第1-2部分 一般要求 受控阻抗　IEC 61188-1-.pdf（46页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARD Printed boards and printed board assemblies - Design and use - Part 1-2: Generic requirements - Controlled impedance The European Standard EN 611881-2:1998 has the status of a British Standard ICs 31.180 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW BS EN 61

2、188-1-2:1998 IEC 61 188-1-2: 1998 STD.BS1 BS EN bllB-L-Z-ENGL 1778 = Lb2qbbS 073b550 b52 Amd. No. BS EN 61188-1-2:1998 Date Text affected This British Standard, having been prepared under the direction of the Electrotechnicai Sector Committee, was published under the authority of the Standards Commi

3、ttee and comes into effect on 15 December 1998 O BSI 1998 ISBN O 680 30668 6 National foreword This British Standard is the English language version of EN 611881-21998. It is identical with IEC 611881-2:1998. The UK participation in its preparation was entrusted to Technical Committee EPYSO1, Electr

4、ical assembly technology, which has the responsibility to: - aid enquirers to understand the text; - present to the responsible internationaUEuropean committee any enquiries on the interpretation, or proposals for change, and keep the UK inkrests informed, - monitor related international and Europea

5、n developments and promulgate them in the UK. A list of organizations represented on this committee can be obtained on request to its secretary. From 1 January 1997, all IEC publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a p

6、eriod of time during the change over from one numbering system to the other, publications may contain identifiers Com both systems. Cross-references Attention is drawn to the fact that CEN and CENELEC standasds normally include an annex which lists normative references to internaiional publications

7、with their corresponding European publications. The British Standards which implement these international or European publications may be found in the BSI Standards Catalogue under the section entitled “International Standarcls Correspondence Index”, or by using the “Find” faciliQ of the BSI Standar

8、ds Electronic Catalogue. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages

9、 This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 43 and a back cover. Amendments issued since publication EUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN 61188-1-2 August 1998 ICs 31.180 English version Printed boards and printed board assemblies - De

10、sign and use Part 1-2: Generic requirements - Controlled impedance (IEC 61 188-1-2:1998) Cartes imprimes et cartes imprimes quipes - Conception et utilisation Partie 1-2: Prescriptions gnriques Impdance contrle Definierte Impedanz Leiterplatten und Flachbaugruppen Konstruktion und Anwendung Teil 1 -

11、2: Allgemeine Anforderungen (CE1 61 188-1 -2: 1998) (IEC 61 188-1 -2:1998) This European Standard was approved by CENELEC on 1998-08-01. CENELEC members are bound to comply with the CENICENELEC Internal Regulaticns which stipulate the conditions for giving this European Standard the status of a nati

12、onal standard without any alteration. Up-to-date lists and bibliographical references concerning such ?national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version

13、in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnicai committees of Austria, Belgium, Czech Republic, Denmark

14、, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnis

15、che Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 1998 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. NO. EN 61 188-1-21998 E STD.BSI BS EN bLL-L-2-ENGL 1998 = Lb24bb9 073b552 425 M Page 2 EN 61 188- 1-2:1998 Forewo

16、rd The text of document 52/758/FDIS, future edition 1 of IEC 61 188-1-2, prepared by IEC TC 52, Printed circuits, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61 188-1-2 on 1998-08-01. The following dates were fixed: - latest date by which the EN has to be impleme

17、nted at national level by publication of an identical national standard or by endorsement (dop) 1999-05-01 - latest date by which the national standards conflicting with the EN have t be withdrawn (dow) 2001 -05-01 Annexes designated “normative“ are part of the body of the standard. Annexes designat

18、ed “informative“ are given for information only. In this standard, annex ZA is normative and annex A is informative. Annex ZA has been added by CENELEC. Endorsement notice The text of the International Standard IEC 61 188-1 -2:1998 was approved by CENELEC as a European Standard without any modificat

19、ion. Page 3 EN 61188-1-2:1998 CONTENTS INTRODUCTION Ciaure scope . Normative references Engineering design overview . 3.1 Device selection . 3.2 Intraconnection 3.3 Printed board and printed board assemblies . 3.4 Performance requirements . 3.5 Power distribution Design of controlled impedance circu

20、its 4.1 Configurations . 4.2 Equations 4.3 Controlled impedance design rules . 4.4 Cross-talk rules . 4.5 Coupon design rules 4.6 Decouplingkapacitor rules . 5.1 Process rules in CAD . 5.2 Design complexity and correlation to cost . Data description 6.1 Details of construction 6.3 Electrical perform

21、ance . Material 7.1 Resin systems . 7.2 Reinforcements 7.3 Prepregs, bonding layers and adhesives 7.4 Frequency dependence Fabrication . 8.1 General . 8.2 Preproduction processes 8.3 Production processes . Design for manufacturing 6.2 Isolation of data by net class (noise, timing. capacitance and im

22、pedance) . 8.4 Impact of defects at high frequencies . 8.5 Data description . Time domain reflectometry (TDR) testing 9.1 Rationale . Annex A . Units. symbols. and terminology Annex ZA Normative references to international publications with their corresponding European publications 0 BSI 1998 Page 4

23、 5 5 5 5 6 7 9 19 20 20 21 24 25 26 28 30 30 30 30 31 31 32 32 32 32 33 33 33 33 34 36 38 40 40 40 42 43 STD-BSI BS EN bLL-L-Z-ENGL L99B I Lb24bb9 0736554 2TB Page 4 EN 61188-1-2:1998 INTRODUCTION Packaging of electronic equipment has traditionally been an area for mechanical considerations. Packagi

24、ng design is becoming more complex as todays electronics technologies are available in greater switching speed and higher density per chip. Individual chips have greater numbers of connections in smaller chip package sizes. To take maximum advantage of device density and speed, designers must pay mu

25、ch more attention to problems of electromagnetic wave propagation phenomena associated with transmission of switching signals within the system. New design disciplines and design strategies are needed. Controlled impedance printed boards are a part of this strategy. Interconnection and the packaging

26、 of electronic components primarily have been the domain of mechanical designers who were concerned with such factors as weight, volume, power, and form factor and with interconnections specified in wire listing or net lists. Electrical conductors for signal transmission were routed with only a few

27、concerns, that continuity was maintained between points, conductors had sufficient copper for the current and clearance was maintained to prevent voltage breakdown. Aside from providing a good electrical path, the electrical performance of the signal was not a major concern. Advances in digital inte

28、grated circuits introduce new devices with extremely fast rise times which are housed in high density microelectronic packages. In order to optimize system performance, these devices require a wiring technology that supports high density interconnection and, at the same time, provides superior elect

29、rical performance. While many system problems are associated with high speed digital processing, none has received more attention than interconnection. It is evident that as system speeds increase, interconnection, packaging, and printed boards become the bottlenecks that slow system performance. Sy

30、stems using 100 K ECL circuitry have almost 55 % of the system delay in the packaging and interconnect. CMOS is normally considered a “slow“ technology, but is designed into system clock rates in excess of 100 MHz. In these cases, not only is system delay a problem but signal attenuation becomes an

31、issue with the low powered, low voltage, lower noise margin BiCMOS devices. Page 5 EN 61188-1-2:1998 PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES - DESIGN AND USE - Part 1-2: Generic requirements - Controlled impedance 1 Scope This part of IEC 61188 is intended to be used by circuit designers, packag

32、ing engineers, printed board manufacturers and procurement personnel so that all may have a common understanding of each area. The aim in packaging is to transfer a signal from one device to one or more other devices through a conductor. High-speed designs are defined as designs in which the interco

33、nnecting properties affect circuit performance and require unique considerations. 2 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this part of IEC 61 188. At the time of publication, the editions indicated we

34、re valid. All normative documents are subject to revision, and parties to agreements based on this part of IEC 61188 are encouraged to investigate the possibility of applying the most recent editions of the normative documents listed below. Members of IEC and IS0 maintain registers of currently vali

35、d international standards. IEC 61 182 (all parts), Printed boards - Electronic data description and transfer IEC 61 182-1:1994, Printed boards - Electronic data description and transfer - Part 1: Printed board description in digital form IEC 61 189-3: 1997, Test methods for electrical materials, int

36、erconnection structures and assemblies - Part 3: Test methods for interconnection structures (printed boards) 3 Engineering design overview 3.1 Device selection Device technology options include TTL, Schottky TTL, CMOS, ECL and GaAs, each with its own set of power requirements, operating temperature

37、 range, density of chip, input impedance, output impedance, signal threshold levels, noise sensitivity, response time and output pulse rise/fall time. Many designs will have mixed technology where SMT and through hole packaging is intermixed with TTL, CMOS and ECL logic that may require multiple lin

38、e widths (impedance values) on the same circuit layer or may compromise on a single conductor width that can provide enough margin for the different logic families. STD-BSI BS EN bLlAA-l-2-ENGL 1998 m Lb24bb7 073b55b O70 m Page 6 EN 61 188- 1-2: 1998 Chips can be individually mounted on a large boar

39、d or assembled into small boards or multichip modules mounted onto large boards. Large systems may require several large board assemblies with another level of interconnection. Noise, timing, and signal degradation will accompany transitions from one packaging level to the next. The electrical conne

40、ctions to the board can be of a variety of configurations ranging from pins that will insert through plated holes in the board, as in dual in-line packages, to a series of lands for surface mount devices. Requirements for component packaging are dependent on many factors including space, economics,

41、electrical performance and reliability, as well as the predominant packaging style of the assembly. The components shall be provided in a style that is compatible with the assembly processes used to manufacture the printed board assembly. The component package shall be considered when designing for

42、high speed. In passive components the predominant factor will be the lead length as leads provide additional inductance and capacitance that will affect propagation speed and switching transients. To minimize these effects the leads may be as short as possible or removed. Surface mount devices can p

43、rovide leadless packages which can be directly mounted to the interconnecting substrate. NOTE - Component data sheets often do not provide parasitic values for high speed noise and propagation speed consideration. Active devices, components such as integrated circuits, are often offered in several p

44、ackages. In general, DIP packages, in either plastic or ceramic, have been the predominate package . These are typically the largest packages and provide the poorest high speed operating environment due to lead configuration. The next best package style is the surface mount package. These are offere

45、d in a variety of packages such as SOICs, PLCCs, PFQPs, TSOPs BGAs. These packages will typically reduce the lead capacitance and inductance. To obtain the optimum performance from the device, the die can be directly mounted to the substrate using either the chip-on-board (COB), flip chip or tape au

46、tomated bonding (TAB) approach. These offer an optimum approach since they minimize the lead capacitance/ inductance. 3.2 Intraconnection 3.2.1 Connectors Intraconnectionc are often troublesome in high speed application because a continuous signal environment is not provided. Most board to board con

47、nector systems are not designed for use in high performance applications and compromise the signal integrity of the system. Board to board connections often mismatch the characteristic impedance designed into the board themselves. There are two primary approaches to reduce the signal discontinuity c

48、aused by interconnect systems: a) The first approach is to provide a connector style such that the pinouts can be arranged to provide a good signal path. Non-differential signals shall establish a relationship between the active signal line and the closest reference plane connection, either a voltag

49、e or ground plane. Non-differential signal conductors rely on controlled geometries and nearby reference plane for impedance control. Signal pin quality, reference pin quality and their location controls electrical performance. To optimise performance, reference pins shall be added to reduce the cross-talk problems. Generally a 3:l ratio of signal to reference pins (.e. 3 signal, 1 reference) is sufficient; Page 7 EN 61188-1-2:1998 b) The second approach is to modify the connector to minimize the discontinuity. By shortening the pin length, or adding a reference ground p