ECA EIA-970-2013 Test Procedure for High Frequency Characterization of Low Inductance Multilayer Ceramic Chip Capacitors.pdf

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1、 EIA STANDARD Test Procedure for High Frequency Characterization of Low Inductance Multilayer Ceramic Chip Capacitors EIA-970 July 2013 EIA-970ANSI/EIA-970 Approved: July 29, 2013 NOTICE EIA Engineering Standards and Publications are designed to serve the public interest through eliminating misunder

2、standings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect pre

3、clude any member or nonmember of ECIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than ECIA members, whether the standard is to be used either domestic

4、ally or internationally. Standards and Publications are adopted by ECIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, ECIA does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the Standa

5、rd or Publication. This EIA Standard is considered to have International Standardization implication, but the International Electrotechnical Commission activity has not progressed to the point where a valid comparison between the EIA Standard and the IEC document can be made. This Standard does not

6、purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the applicability of regulatory limitations before its use. (From Stan

7、dards Proposal No. 5225, formulated under the cognizance of the P-2.1 Committee on EIA National Ceramic and Dielectric Capacitors Standards). Published by Electronic Components Industry Association 2013 Engineering Department 2214 Rock Hill Road, Suite 170 Herndon, VA 20170 PLEASE! DONT VIOLATE THE

8、LAW! This document is copyrighted by the ECIA and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: IHS 15 Inverness Way East Englewood, CO 80112-5704 or call USA

9、and Canada (1-877-413-5184), International (303-397-7956) i CONTENTS Page Foreword ii Clause 1 Scope 1 2 Summary of test method 1 3 Application of test method 2 4 Symbols and equations of circuit elements 3 5 Test equipment 5 6 Test method 9 7 Comments 16 Figures 1 Measurement overview 2 2 S paramet

10、er vector diagram 4 3 Measurement setup 5 4 Top view of test fixture 6 5 Cross section view of test fixture 6 6 Top view of probe pads 7 7 Test fixture and capacitor assembly 8 8 Short calibration 9 9 Load calibration 9 10 Thru calibration 10 11 Test fixture with shorted capacitor pads 11 12 S21 and

11、 equivalent circuit for shorted fixture 11 13 Measurement of component on test fixture 12 14 S21 and equivalent circuit for capacitor and fixture 12 15 Capacitor equivalent circuit 13 16 Measured and curve fit impedance of capacitor 13 ii Foreword (From Standards Proposal No. 5225, formulated under

12、the cognizance of the P-2.1 Committee on EIA National Ceramic and Dielectric Capacitors Standards). EIA-970 Page 1 1 Scope This test method is used to measure the S parameters of low-inductance multilayer ceramic capacitors when mounted in shunt on a probeable low inductance test fixture. 2 Summary

13、of test method The test method can be used to characterize low inductance capacitors. The output of this specification is a frequency independent lumped element representation of a capacitor consisting of three elements, equivalent series capacitance (ESC), equivalent series resistance (ESR) and equ

14、ivalent series inductance (ESL) applicable in the range of 30 kHz to 3 GHz. The test method is summarized below. a) The measurements are performed on a vector network analyzer (VNA) in the frequency range from 30 kHz to 3 GHz. b) The measurement is a two port shunt configuration, utilizing probeable

15、 calibration substrates and probeable test fixtures. c) During characterization, the capacitor is assembled to a test fixture. d) The effects of the test fixture must be compensated by the use of a de-embedding technique. e) Equivalent series capacitance (ESC) is extracted from the de-embedded data

16、in the frequency range of 30 kHz to the resonance frequency. f) Equivalent series resistance (ESR) is extracted from the de-embedded data at the resonance frequency. g) Equivalent series inductance (ESL) is extracted from the de-embedded data in the frequency range from the resonance frequency to 3

17、GHz. h) The additional result of this measurement is to provide the S Parameter data for the component for use in design and circuit simulation of the microprocessor board application. Figure 1 provides a schematic overview of the test method. EIA-970 Page 2 MeasureShorted FixtureMeasure FixtureAnd

18、CapacitorS Parameter MeasurementVector Network AnalyzerFixture ModelsFixture and Capacitor ModelsDe-Embed Fixture ContributionCalibrationSOLTCapacitorParametersCurve Fit De-Embedded S ParametersFigure 1 - Measurement overview 3 Application of test method a) The application of the test device is for

19、decoupling and charge storage at the first level connection to the microprocessor and for charge storage at the second level of power supply connection to the microprocessor board. b) This measurement can be applied to any multilayer capacitor chip. It can be applied to any passive device in general

20、 with consideration for the properties and design of the device. c) The output of this specification is a frequency independent lumped element model consisting of three elements. However, not all capacitors can be described by a three element model. The user must decide if the three element model is

21、 an appropriate representation of the capacitor behavior for the device being examined. d) This method may be used as when the following criteria are satisfied, 2. ESR 3 mOhmGHz3ESCESL21kHz30 .1EIA-970 Page 3 4 Symbols and equations of circuit elements The following section contains definitions of s

22、ymbols and terminology as used in this specification. Decibels (dB): the logarithmic ratio of a voltage to a reference or input voltage expressed as, =ViVo20logdB10Decibel Conversion Milliwatts (dBm): Decibels relative to one milliwatt, =1mWSignal(mW)10logdBm10DUT: Device under test. EDA: Electronic

23、 Design Automation. Equivalent series capacitance (ESC): ESC is the circuit capacitance of a series combination of C, L and R that are used to approximate the behavior of the device over a range of frequency. Equivalent series inductance (ESL): ESL is the circuit inductance of a series combination o

24、f C, L and R that are used to approximate the behavior of the device over a range of frequency. Equivalent series resistance (ESR): ESR is the circuit resistance of a series combination of C, L and R that are used to approximate the behavior of the device over a range of frequency. Impedance (Z): Fo

25、r a 2 port measurement with a DUT in shunt, the impedance of the DUT can be expressed by the following equation, where both Z and S21are complex values, 1S25SZ2121=S Parameter: Scattering parameters are used to characterize a two port device. S Parameters are determined by measuring magnitude and ph

26、ase of incident, reflected and transmitted voltage signals. The S Parameter vector diagram in Figure 2 illustrates the following definitions. 01022211=aaababIncidentReflectedSIncidentReflectedS221101022112=aaababIncidentdTransmitteSIncidentdTransmitteS1221EIA-970 Page 4 2 Port DeviceS11b1ReflectedS2

27、1b2Transmitteda1IncidentS22b2ReflectedS12b1Transmitteda2IncidentPort 1 Port 2Figure 2 S parameter vector diagram Series equivalent circuit quantities: Derived quantities are used to characterize the electrical characteristics of series equivalent circuits. Series resonance frequency (SRF): SRF is th

28、e frequency at which there is cancellation of the inductive and reactive elements of the circuit. VNA: The vector network analyzer (VNA) is used to measure the S parameters by applying a test signal to the DUT ports and measuring the reflected and transmitted signals. EIA-970 Page 5 5 Test equipment

29、 5.1 Equipment list and setup An equipment list is provided and an example test setup is shown in Figure 3. a) Vector Network Analyzer, Agilent 8753ES or equivalent, meeting the following specifications, 1) test frequency range: 30 kHz to at least 3 GHz with a logarithmic frequency sweep is suggeste

30、d; 2) signal level: set to 0 dBm; 3) detection level: -80 dBm minimum; b) Probe Station, Cascade Summit or equivalent; c) Two SMA cables, Gore FB Microwave Test Assembly, or equivalent; d) A pair of RF microwave probes, Cascade ACP40-GS-250 and ACP40-SG-250 or equivalent; e) Probeable calibration su

31、bstrate, Cascade P/N 103-726 or equivalent for selected RF microwave probes; f) 5/16 torque wrench, 5 in/lb for SMA connectors; g) Universal Capacitor Test Fixture, Ibiden P/N D50230-001 or equivalent. Figure 3 Measurement setup EIA-970 Page 6 5.2 Test fixture The test fixture is a probeable two lay

32、er low inductance test substrate, as shown in Figure 4. a) The test fixture consists of an outer, or surface, layer containing the capacitor pads and probe pads. The outer layer is a solid metal plane which connects the positive terminal(s) of the capacitor to the positive terminal of the probe pads

33、. The outer plane contains voiding to allow for the negative terminal(s) of the capacitor and probe pad. b) The test fixture consists of an inner layer, which is a solid metal plane used to make the connection between the negative terminals and probe pads. Probe pads300 um300 umOuter LayerInner Laye

34、r600 um300 umAABBCap bodyCap padsViasFigure 4 Top view of test fixture c) Figure 5 shows a cross section view of the test structure. Typical metal thickness is 15 microns. Typical dielectric thickness is 30 microns. Typical dielectric constant 3.4. CapacitorSolder FilletOuter LayerInner LayerProbe a

35、reaView B-BCapacitor-+CapacitorView A-AFigure 5 Cross view of test fixture EIA-970 Page 7 d) Figure 6 illustrates a preferred probe pad design. The negative pad is designed to be larger in size than the positive pad to allow for vias in pad. The number of vias within the probe and capacitor pads sho

36、uld be maximized to reduce inductance. The recommended test pads require the use microwave probes with a pitch of 250 um between signal and ground. 50 um Pad to PadPositive NegativeProbe Touch Down AreaVia Keepout300 umProbe Touch Down AreaVia Keepout300 umVia Area250 um (ref)Metal PadSolder ResistO

37、peningFigure 6 Top view of probe pads Metal Pad Solder Resist Opening Positive Pad 260 x 1860 um 200 x 1800 um Negative Pad 460 x 1860 um 400 x 1800 um Table 1 Probe pad dimensions EIA-970 Page 8 5.3 Test fixture and capacitor assembly Figure 7 illustrates the final test configuration. The test conf

38、iguration consists of an MLCC assembled to the test fixture. RF microwave probes are used contact the probe pads. Figure 7 illustrates the final location of the probes on the probe pads. Figure 7 Test fixture and capacitor assembly EIA-970 Page 9 6 Test method 6.1 VNA calibration, SOLT full 2-port c

39、alibration method 6.1.1 Probe and connector type The recommended test pads require the use of microwave probes with a pitch of 250 um between signal and ground. One probe should be a signal ground (SG) configuration. The second probe should be a ground signal (GS) configuration. This specification d

40、escribes the calibration procedure for Cascade RF microwave probes. Follow the manufacturers recommendations if using probes from another manufacturer. 6.1.2 Calibration substrate A calibration substrate is required to calibrate to the end of the probe tips. Select a calibration substrate designed t

41、o support a Short-Open-Load-Thru (SOLT) calibration. Follow the manufacturers recommendations for calibration coefficients. 6.1.3 Reflection calibration- ports 1 and 2 a) Land the probes on the short calibration structure, as shown in Figure 8, and perform short circuit calibration. GSGSGSFigure 8 S

42、hort calibration b) Raise the probes in the air, so that no contact is made to the calibrate substrate. Perform the open circuit calibration. c) Land the probes on the load calibration structure, as shown in Figure 9, and perform load circuit calibration. GSGSGSFigure 9 Load calibration EIA-970 Page

43、 10 6.1.4 Isolation calibration Not required. 6.1.5 Thru calibration a) Land the probes on the thru calibration structure, as shown in Figure 10. GSGSGSFigure 10. Thru calibration b) Measure forward transmission thru. c) Measure forward match thru. d) Measure reverse transmission thru. e) Measure re

44、verse match thru. f) Complete calibration and save data. g) Verify calibration through measurement of a known DUT. h) System is ready to perform measurements. EIA-970 Page 11 6.2 Fixture characterization The fixture contribution is estimated by measuring the fixture in a shorted configuration. An il

45、lustration of the shorted fixture is shown in Figure 11. Figure 11 Test fixture with shorted capacitor pads Characteristics of the fixture are measured as described below. a) It is preferable to include a shorted test structure in the design of the test fixture. If this is not available, the test fi

46、xture may be shorted by carefully applying a solder short to the capacitor pads. b) S11, S22, S12and S21of the shorted fixture are measured. c) Figure 12 illustrates a representative S21response and equivalent circuit. d) The equivalent circuit reflects the test fixture design in Section 5.2. If an

47、alternate test fixture is utilized, the user should verify the equivalent circuit. Figure 12 S21 and equivalent circuit for shorted fixture e) The impedance of the fixture is calculated from the following formula, where Z and S21are complex values, 1S25SZ2121fixture=EIA-970 Page 12 6.3 Component and

48、 fixture measurement The component is characterized by measuring the capacitor assembled on the test fixture. This is illustrated in Figure 13. Figure 13 - Measurement of component on test fixture Characteristics of the capacitor and fixture measurement are described below. a) Component is mounted o

49、n test substrate. b) S11, S22, S12and S21of the capacitor and fixture are measured. c) Figure 14 illustrates a representative S21response and equivalent circuit. Figure 14 - S21 and equivalent circuit for capacitor and fixture d) The impedance of the capacitor and fixture is calculated from the following formula, where Z and S21are complex values, 1S25SZ2121fixturecapacitor=+EIA-970 Page 13 6.4 Overview of de-embedding and parameter extraction De-embedding is used to compensate for the fixture contribution in the meas