DLA SMD-5962-97545 REV E-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 512K x 16-BIT x 2-BANK SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MONOLITHIC SILICON《单片硅同步动态随机存储器(SDRAM) 512K x.pdf

《DLA SMD-5962-97545 REV E-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 512K x 16-BIT x 2-BANK SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MONOLITHIC SILICON《单片硅同步动态随机存储器(SDRAM) 512K x.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-97545 REV E-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 512K x 16-BIT x 2-BANK SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MONOLITHIC SILICON《单片硅同步动态随机存储器(SDRAM) 512K x.pdf（51页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate. Added device type 03 to drawing. Changed tAPWminimum limits from 75ns and 100 ns to the quantity tRP+ tCK. Removed all references to nBSDfrom drawing. - glg 98-01-20 Raymond Monnin B Changes in accordance with NOR 5962-R071-9

2、8. - glg 98-03-19 Raymond Monnin C Changes to paragraph 1.3 and 1.4. Table IA changes to IL, IO, ICC2N, ICC3P, ICC3PS, ICC3N, ICC4, and ICC5. Removed number of cycles table from Table IA, sheet 12. - glg 99-03-16 Raymond Monnin D Change CAGE code to correct CAGE of 67268. Update to current boilerpla

3、te. Editorial changes throughout. - gap 02-04-02 Raymond Monnin E Boilerplate update and part of five year review. tcr 07-12-13 Robert M. Heber REV E E E E E E E E E E E E E E E E SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 REV E E E E E E E E E E E E E E E E E E E E SHEET 15 16 17 18 19 2

4、0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bow

5、ling THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-06-17 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K x 16-BIT x 2-BANK, SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM), MONOLITHIC SILICON AMSC N/A REV

6、ISION LEVEL E SIZE A CAGE CODE 67268 5962-97545 SHEET 1 OF 50 DSCC FORM 2233 APR 97 5962-E096-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990

7、REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case ou

8、tlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application env

9、ironment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97545 01 Q X A | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2

10、.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designato

11、r. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 626162-15 512K word x 16 bit x 2 bank, synchronous DRAM 15 ns 02 626162-20 512K word x 16 bit x 2 bank, synchronous

12、DRAM 20 ns 03 626162-12 512K word x 16 bit x 2 bank, synchronous DRAM 12 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements

13、 for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a nontraditional performance environment (encapsulated in plastic) Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case o

14、utline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 50 Ceramic dual flat pack Y See figure 1 50 Plastic TSOP(II) package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for d

15、evice classes N, Q, and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET

16、 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range, (VCC) -0.5 V dc to +4.6 V dc Supply voltage range for output drivers, (VCCQ) -0.5 V dc to +4.6 V dc Voltage range on any input pin . -0.5 V dc to +4.6 V dc Voltage range on any output pin . -0.5 V dc to VCC+0.5 V dc S

17、hort-circuit output current 50 mA Power dissipation 1 W Operating free-air temperature range, (TA) . -55C to +125C Storage temperature range, (Tstg) . -65C to +150C Junction temperature, (TJ) +175C Thermal resistance, junction-to-case, (JC): Case X +5C/W Case Y +1C/W 1.4 Recommended operating condit

18、ions. 2/ Supply voltage range, (VCC) +3.135 V dc to +3.465 V dc Supply voltage for output drivers, (VCCQ) . +3.135 V dc to +3.465 V dc 3/ Supply voltage, (VSS) 0 V dc Supply voltage for output drivers, (VSSQ) 0 V dc High-level input voltage, (VIH) +2.0 V dc to VCC+0.3 V dc Low-level input voltage, (

19、VIL) . -0.3 V dc to +0.8 V dc Operating free-air temperature, (TA) . -55C to +125C 1.5 Digital logic testing for device classes N, Q, and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) 100 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards,

20、 and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated C

21、ircuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended op

22、eration at the maximum levels may degrade performance and affect reliability. 2/ All voltage values in this drawing are with respect to VSS. 3/ VCCQ VCC+0.3 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

23、97545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs). MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online a

24、t http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein,

25、the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with M

26、IL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535

27、, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and V or MIL-PRF-38535, appendix A and herein for de

28、vice class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Output load circuit. The o

29、utput load circuit shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipm

30、ent limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or aquiring activity upon request. For devi

31、ce class Q and V, alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or aquiring activity upon request. 3.3 Electrical performance characteristics and postirradiati

32、on parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements sh

33、all be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not fe

34、asible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall b

35、e in accordance with MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.

36、5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes N, Q, and V

37、, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply

38、in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes N, Q, and V, the requirements of MIL-PRF-38535 and herein or for device class

39、 M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this

40、 drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class

41、 M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M

42、devices covered by this drawing shall be in microcircuit group number 41 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes N, Q, and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacture

43、rs Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes N, Q, and V, screening sha

44、ll be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspect

45、ion. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table II herein. b. The test circuit shall be maintained by the man

46、ufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (1) Dynamic burn-

47、in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein). c. Interim and final electrical parameters shall be as specified in table II herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

48、 A 5962-97545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TA +125C +3.135 V VCC +3.465 V Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max High-level output voltage VOHIOH = -2 mA 1,2,3 All 2.4 V Low-level output voltage VOLIOL = +2 mA 1,2,3 All 0.4 V Input current (leakage) II0 V Vl VCCAll other pins = 0 V to VCC1,2,3 All 10 A Output current (leakage) IO0 V VO VCCQOutput disabled 1,2,3