DLA SMD-5962-96840 REV A-2005 MICROCIRCUIT DIGITAL MEMORY RADIATION HARDENED CMOS 4 X 32K X 40 SRAM MULTICHIP MODULE (MCM)《4 X 32K X 40静态存储器多片组件硅单片电路数字记忆微电路》.pdf

《DLA SMD-5962-96840 REV A-2005 MICROCIRCUIT DIGITAL MEMORY RADIATION HARDENED CMOS 4 X 32K X 40 SRAM MULTICHIP MODULE (MCM)《4 X 32K X 40静态存储器多片组件硅单片电路数字记忆微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96840 REV A-2005 MICROCIRCUIT DIGITAL MEMORY RADIATION HARDENED CMOS 4 X 32K X 40 SRAM MULTICHIP MODULE (MCM)《4 X 32K X 40静态存储器多片组件硅单片电路数字记忆微电路》.pdf（26页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-12-08 Thomas M. Hess REV SHET REV A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

2、PMIC N/A PREPARED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, MEMORY, RADIATION HAR

3、DENED, CMOS, 4 X 32K X 40 AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-10-07 SRAM, MULTICHIP MODULE (MCM) AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-96840 SHEET 1 OF 25 DSCC FORM 2233 APR 97 5962-E511-05 Provided by IHSNot for ResaleNo reproduction or networking perm

4、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (dev

5、ice classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as show

6、n in the following example: 5962 - 96840 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices me

7、et the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The

8、 device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 HX84050 4 X 32K X 40 CMOS, SOI, SRAM, Multichip Module (MCM) 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Devi

9、ce class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) ar

10、e as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 200 Quad flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by

11、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Storage temperature range.

12、 -65C to +125C Supply voltage range (VDD). -0.5 V dc to 6.5 V dc DC input voltage range (VIN). -0.5 V dc to VDD+ 0.3 V dc DC output voltage range (VOUT) -0.5 V dc to VDD+ 0.3 V dc Output voltage applied to high-Z state -0.3 V dc to VDD+ 0.3 V dc Maximum power dissipation (PD) 5.6 W 3/ Lead temperatu

13、re (soldering, 10 seconds) +288C Chip thermal resistance, junction-to-case (JC). 4.0C/W 4/ Maximum junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VDD). 4.5 V dc to 5.5 V dc Supply voltage (VSS) . 0.0 V dc High level input voltage range, CMOS levels (VIH)

14、0.7 VDDto VDD+ 0.3 V dc Low level input voltage range, CMOS levels (VIL). -0.3 V dc to 0.3 VDDModule thermal resistance, junction-to-case (JC) 1.0C/W (module power) 4/ Case operating temperature range (TC) -55C to +125C 1.5 Radiation features. Maximum total dose available (dose rate = 50 300 rads(Si

15、)/s) 1 x 106rads(Si) 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the soli

16、citation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT

17、OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbi

18、ns Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to VSS(V

19、SS= ground). 3/ Maximum power dissipation with 20 chips utilized at 50 percent (each subsystem is maximum utilized, alternating between banks) and outputs loaded as in figure 5. 4/ Assumes a uniform temperature on the bottom surface of the package, and a uniform power distribution over the top surfa

20、ce of the die, and all die at equal power level. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2

21、.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. AMERICAN SOCIAETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - The Measurem

22、ent of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Application for copies should be addressed to ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959) ELECTRONIC INDUSTRIES ALLIANCE (EIA) JESD 78 - IC Latch-up Test (Applications

23、for copies should be addressed to Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document

24、, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manuf

25、acturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.

26、 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance w

27、ith 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4. 3.2.5 Timing waveforms and output loa

28、d circuit. The timing waveforms and output load circuit shall be as specified on figure 5. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 6. 3.2.7 Functional test. Various functional tests used to test this device are contained in the appendix. If th

29、e test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to t

30、he preparing or acquiring activity upon request. For device classes Q and V alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3

31、.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. Provided by I

32、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requireme

33、nts shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is

34、not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall

35、 be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certifica

36、te of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order t

37、o be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-

38、PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lo

39、t of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review

40、for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment

41、 for device class M. Device class M devices covered by this drawing shall be in microcircuit group number H41 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUP

42、PLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Limits Test Symbol Conditions 1/ -55C TC+125C 4.5 V VDD 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit High level output voltage

43、 VOHVDD= 4.5 V, IOH= -3.5 mA, VIH= 3.15 V, VIL= 1.35 V 1, 2, 3 All 4.2 V Low level output voltage VOLVDD= 4.5 V, IOL= 7.0 mA, VIH= 3.15 V, VIL= 1.35 V 1, 2, 3 All 0.4 V High level input leakage current IIHVDD= 5.5 V, VIN= VDD, all other pins = VSS1, 2, 3 All -50 50 A Low level input leakage current

44、IILVDD= 5.5 V, VIN= VSS, all other pins = VDD1, 2, 3 All -50 50 A High level output leakage current IOZHVDD= 5.5 V, VIN= VDD, all other pins = VSS1, 2, 3 All -50 50 A Low level output leakage current IOZLVDD= 5.5 V, VIN= VDD, all other pins = VDD1, 2, 3 All -50 50 A Data retention voltage VDRVDD= 2.

45、5 V 1, 2, 3 All 2.5 V Operating supply current ICC1CS= VSS, CE = VDD, VDD= 5.5 V, f = 20 MHz 2/ 1, 2, 3 All 525 mA Supply current, deselected ICC2CS = CE = VDD, VDD= 5.5 V, f = 20 MHz 2/ 1, 2, 3 All 30 mA Supply current, standby ICC3CS = CE = VDD, VDD= 5.5 V, f = 0.0 MHz 2/ 1, 2, 3 All 30 mA Supply

46、current, disabled ICC4CS = CE = VSS, VDD= 5.5 V, f = 20 MHz 2/ 1, 2, 3 All 30 mA Supply current, disabled, idle ICC5CS = CE = VSS, VDD= 5.5 V, f = 0.0 MHz 2/ 1, 2, 3 All 30 mA Data retention current ICC6VDD= 2.5 V, VIN= 2.5 V 1, 2, 3 All 10 mA Input capacitance, CS and CE inputs 3/ CIN1VIN= VDDor VS

47、S, f = 1.0 MHz, TA= +25C 4 All 50 pF Input capacitance, address, OE, and WE inputs 3/ CIN2 VIN= VDDor VSS, f = 1.0 MHz, TA= +25C 4 All 70 pF Output capacitance 3/ COUTVOUT= VDDor VSS, f = 1.0 MHz, TA= +25C 4 All 26 pF Functional tests See 4.4.1c 7, 8 All See footnotes at end of table. Provided by IH

48、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96840 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TC+125C 4.5 V VDD 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit READ CYCLE Read cycle time tAVAV9, 10, 11 All 30 ns Address access time tAVQV9, 10, 11 All 26 ns Chip enable/select access time tEHQV, tSLQV 9, 10, 11 All 30 n