DLA SMD-5962-96836 REV A-2002 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 2000 GATES MONOLITHIC SILICON《互补金属氧化物半导体可编程与门排列2000门硅单片电路数字记忆微电路》.pdf

《DLA SMD-5962-96836 REV A-2002 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 2000 GATES MONOLITHIC SILICON《互补金属氧化物半导体可编程与门排列2000门硅单片电路数字记忆微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96836 REV A-2002 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 2000 GATES MONOLITHIC SILICON《互补金属氧化物半导体可编程与门排列2000门硅单片电路数字记忆微电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-05-08 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DE

2、FENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 98-03-31 MICROCIRCUIT, MEMORY

3、, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY 2000 GATES, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-96836 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E382-02 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo

4、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96836 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels cons

5、isting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the

6、PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 96836 01 M X X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device class

7、es Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA d

8、evice. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Delay Factor (K) Min Max 01 QL12X16B-0 2000 Gate CMOS FPGA 0.39 1.82 02 QL12X16B-1 2000 Gate CMOS FPGA 0.39 1.56 1.2.3 Device class designator. The device class desig

9、nator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification

10、 and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-PN 84 Pin grid array 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for devi

11、ce classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Actual number of pins is 85, including one index or orientation pin (C3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96836 DEFENSE

12、 SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range (VCC) . -2.0 V dc to +7.0 V dc Programming supply voltage range (VPP) -2.0 V dc to +13.5 V dc DC input voltage range -2.0 V dc to +7.0 V dc Maximum p

13、ower dissipation 2.5 W 3/ Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC): Case outline X . 5.3 C/W Junction temperature (TJ) +175C 4/ Storage temperature range . -65C to +150C Data retention 10 years (minimum) 1.4 Recommended operating conditions. 5/ Case

14、operating temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standar

15、ds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and

16、 supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component

17、Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robb

18、ins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS

19、). 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ All voltage values in this drawing are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted

20、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96836 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.

21、Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DoDISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DoDISS are the issues of the documents cited in the solicitation. ELECTRONIC INDU

22、STRIES ALLIANCE (EIA) JESD 78 - IC Latch-Up Test. (Application for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein,

23、 the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-

24、PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, a

25、ppendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device cl

26、ass M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electr

27、ical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for

28、 each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manuf

29、acturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A

30、. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a

31、certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in M

32、IL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the

33、requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.

34、8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking per

35、mitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96836 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activit

36、y retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in micr

37、ocircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations, two processing options are provided for selection in the contract. 3.11.1 Unprogram

38、med device delivered to the user. All testing shall be verified through group A testing as defined in table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.11.2 Manufacturer-programmed device delivered to the user. All tes

39、ting requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.12 Data Retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test sha

40、ll be done for initial characterization and after any design or process changes which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors procedure sha

41、ll be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with the test data. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF

42、-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening

43、. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all d

44、evices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 5 of table IIA herein. b. T

45、he test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. Test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent s

46、pecified in test method 1015. Use of built-in test circuitry testing the entire lot to verify programmability and AC performance without programming the user array is an option the manufacturer may use. c. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2

47、Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision

48、 level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance w

49、ith the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. Provided by IHSNot for Re