DLA SMD-5962-94690 REV A-2009 MICROCIRCUIT LINEAR 16-BIT 50KHZ ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw. Update drawing to current requirements. drw 09-11-25 Charles F. Saffle REV SHEET REV A SHEET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DEFENSE SUPPLY

2、CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Sandra Rooney APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 16-BIT, 50 KHZ ANALOG TO DIGITAL CO

3、NVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-02-08 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-94690 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E061-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

4、 A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice

5、 of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 94690 01 M X A Federal stock class

6、 designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the a

7、ppropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type G

8、eneric number Circuit function 01 CS5336-T 16-bit, 50 kHz stereo analog to digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to

9、 the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designat

10、or Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

11、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and

12、space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following exampl

13、e: 5962 - 94690 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 sp

14、ecified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies th

15、e circuit function as follows: Device type Generic number Circuit function 01 CS5336-T 16-bit, 50 kHz stereo analog to digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements

16、documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline are as designated in MIL-STD-1835 as

17、follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction

18、 or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q a

19、nd V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall b

20、e in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535

21、, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.3 Electrical

22、performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requ

23、irements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where m

24、arking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-

25、38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in M

26、IL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be

27、required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device cl

28、asses Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, ap

29、pendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects thi

30、s drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the revie

31、wer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

32、DRAWING SIZE A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Resolut

33、ion for which no missing codes is guaranteed RES 1/, 2/ 4, 5, 6 01 16 Bits Dynamic range 1/ 4, 5, 6 01 84 dB Signal-to-(noise + distortion) S/(N+D) 1/ 4, 5, 6 01 82 dB Total harmonic distortion THD 1/ 4, 5, 6 01 0.013 % Interchannel isolation dc 20 kHz 1 / 4, 5, 6 01 83 dB Interchannel gain mismatch

34、 1/ 4, 5, 6 01 0.1 dB Gain error AE 1/ 4, 5, 6 01 6 % Bipolar offset error BPOE1/, 3/ 4, 5, 6 01 65 LSB Input voltage range VIN 1/ 4, 5, 6 01 3.5 V Positive analog supply current IA+ Normal operation 1/ 1, 2, 3 01 35 mA Power-down mode 1/ 50 A Negative analog supply current IA- Normal operation 1/ 1

35、, 2, 3 01 -35 mA Power-down mode 1/ -50 A Positive digital supply current ID+ Normal operation 1/ 1, 2, 3 01 50 mA Power-down mode 1/ 400 A Digital input voltage VIHHigh-level 1, 2, 3 01 70%VD+ V VIL Low-level 30%VD+ Digital output voltage VOHHigh-level at -20 A 1, 2, 3 01 4.4 V VOL Low-level at +20

36、 A 0.1 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Ele

37、ctrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max ICLKD period tCLKW1CMODE low, 4/, 5/ See figure 3 9, 10, 11 01 78 3906 ns tCLKW2CMODE high 5/ See figure 4 52 2604 ICLKD low tCLKL1CMODE

38、low, 5/ See figure 3 9, 10, 11 01 31 ns tCLKL2CMODE high 5/ See figure 4 20 ICLKD high tCLKH1CMODE low, 5/ See figure 3 9, 10, 11 01 31 ns tCLKH2CMODE high 5/ See figure 4 20 ICLKD rising to OCLKD rising tIO1CMODE low, 5/ See figure 3 9, 10, 11 01 5 40 ns ICLKD rising or falling to OCLKD rising tIO2

39、CMODE high 5/, 6/ See figure 4 9, 10, 11 01 5 45 ns ICLKD rising to RL/ edge tILR1CMODE low, MASTER mode See figure 3 5/ 9, 10, 11 01 5 50 ns ICLKD rising to FSYNC edge tIFS1CMODE low, MASTER mode See figure 3 5/ 9, 10, 11 01 5 50 ns ICLKD rising to SCLK edge tISCLK1CMODE low, MASTER mode See figure

40、 3 5/ 9, 10, 11 01 5 50 ns ICLKD falling to RL/ edge tILR2CMODE high, MASTER mode See figure 4 5/ 9, 10, 11 01 5 50 ns ICLKD falling to FSYNC edge tIFS2CMODE high, MASTER mode See figure 4 5/ 9, 10, 11 01 5 50 ns ICLKD falling to SCLK edge tISCLK2CMODE high, MASTER mode See figure 4 5/ 9, 10, 11 01

41、5 50 ns SCLK rising to SDATA valid tSDOMASTER mode, See figure 5 5/ 9, 10, 11 01 0 50 ns tDSSSLAVE mode, See figure 6 5/ 50 SCLK duty cycle MASTER mode 5/ 9, 10, 11 01 40 60 % See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

42、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Group A subgroups Device type Limits Unit unl

43、ess otherwise specified Min Max SCLK rising to RL/ tMSLRMASTER mode 5/ See figure 5 9, 10, 11 01 -20 20 ns SCLK rising to FSYNC tMSFSMASTER mode 5/ See figure 5 9, 10, 11 01 -20 20 ns SCLK period tSCLKWSLAVE mode 5/ See figure 6 9, 10, 11 01 155 ns SCLK pulse width low tSCLKLSLAVE mode 5/ See figure

44、 6 9, 10, 11 01 60 ns SCLK pulse width high tSCLKHSLAVE mode 5/ See figure 6 9, 10, 11 01 60 ns RL/ edge to MSB valid tLRDSSSLAVE mode 5/ See figure 6 9, 10, 11 01 50 ns Falling SCLK to RL/ edge delay tSLR1SLAVE mode 5/ See figure 6 9, 10, 11 01 30 ns RL/ edge to falling SCLK setup time tSLR2SLAVE m

45、ode 5/ See figure 6 9, 10, 11 01 30 ns Falling SCLK to rising FSYNC delay tSFS1SLAVE mode 5/ See figure 7 9, 10, 11 01 30 ns Rising FSYNC to falling SCLK time tSFS2SLAVE mode 5/ See figure 7 9, 10, 11 01 30 ns DPD pulse width tPDWSee figure 8 5/ 9, 10, 11 01 2 X tCLKW ns DPD rising to DCAL rising tP

46、CRSee figure 8 5/ 9, 10, 11 01 50 ns 1/ Logic 0 = GND; Logic 1 = VD+; TA= -55C to +125C; VA+, VL+, VD+ = +5 V; Full-scale input sinewave = 1 kHz; Output word rate = 48 kHz; SCLK = 3.072 MHz; Source impedance = 50 with 10 nF to AGND; Measurement bandwidth is 10 Hz to 20 kHz; unless otherwise specifie

47、d. 2/ Guaranteed by design and or characterization. 3/ After calibration with DCAL connected to ACAL, and ZEROL and ZERROR terminated to AGND with an impedance matched to the AINR and AINL source impedance. Executing a calibration with ACAL tied low will yield an offset error of typically less than

48、5 LSB. 4/ Specifies minimum output word rate (OWR) of 1 kHz. 5/ TA= +25C; VA+, VL+, VD+ = +5 V 5%; VA- = -5 V 5%; Inputs: Logic 0 = 0 V; Logic 1 = VD+; CL= 20 pF. 6/ ICLKD rising or falling depends on DPD to L/R timing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWIN