DLA SMD-5962-94684 REV A-2013 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ALTERABLE FLASH PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to meet current MIL-PRF-38535 requirements. Removed class M references. - glg 13-12-12 Charles Saffle REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13

2、14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICA

3、LLY ALTERABLE FLASH PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-03-14 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-94684 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E089-14 Provided by IHSNot for ResaleNo reproduction or netw

4、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (d

5、evice class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in

6、the following example: 5962 - 94684 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet

7、the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed (MHz) 01 7C371 32 Macrocell CP

8、LD 66 02 7C371 32 Macrocell CPLD 83 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case

9、 outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GQCC1-J44 44 J leaded chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. 1.3 Absolute maximum ratings. 1/ Supply vol

10、tage range (VCC) . -2.0 V dc to +7.0 V dc Programming supply voltage range (VPP) -2.0 V dc to +13.5 V dc 2/ DC input voltage range -2.0 V dc to +7.0 V dc 2/ Maximum power dissipation 2.5 W 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X . S

11、ee MIL-STD-1835 Junction temperature (TJ) +175C 4/ Storage temperature range . -65C to +150C Endurance . 25 erase/write cycles (minimum) Data retention 10 years (minimum) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum level

12、s may degrade performance and affect reliability. 2/ Minimum dc input voltage is -0.5 V, which may overshoot to -2.0 V for periods less than 20 ns. Maximum dc voltage on output pins is VCC+ 0.5 V, which may overshoot to +7.0 V for periods less than 20 ns under load conditions. 3/ Must withstand the

13、added PDdue to short circuit test (e.g., IOS). 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

14、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 5/ Case operating temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) . +4.5 V dc m

15、inimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Input rise time (tR) 100 ns maximum Input fall time (tF) . 100 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The fol

16、lowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing

17、, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcir

18、cuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the

19、extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to JEDEC, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107; http:/w

20、ww.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict

21、between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 5/ All voltage values in this drawing are with respect to VSS. P

22、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item r

23、equirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction,

24、 and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as sp

25、ecified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specif

26、ied in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with t

27、he PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA d

28、esignator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classe

29、s Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawi

30、ng shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this

31、 drawing. 3.8 Processing CPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.8.1 Erasure of CPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.6 herein. 3.

32、8.2 Programmability of CPLDs. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.7 herein. 3.8.3 Verification of erasure or programmed CPLDs. When specified, devices shall be verified as either programmed (see 4.7 herein) to t

33、he specified pattern or erased (see 4.6 herein). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from

34、the lot. 3.9 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and pr

35、ocedures may be vendor specific, but shall guarantee the number of endurance cycles listed in section 1.3 herein over the full military temperature range, and shall be under document control and shall be made available upon request. 3.10 Data Retention. A data retention stress test shall be complete

36、d as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process changes which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over th

37、e full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with the test data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

38、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgroups Device type

39、 Limits Unit Min Max High Level output voltage VOHVCC= 4.5 V, VIL= 0.8V IOH= -2.0 mA, VIH= 2.0 V 1, 2, 3 All 2.4 V Low level output voltage VOLVCC= 4.5 V, IOL= 12.0 mA VIL= 0.8 V, VIH= 2.0 V All 0.5 V High level input voltage 1/ VIHAll 2.0 7.0 V Low level input voltage 1/ VILAll 0.5 0.8 V Input leak

40、age current IIXVCC= 5.5 V, VIN= 0 V and 5.5 V All -10 +10 A Output leakage current IOZVCC= 5.5 V, VIN= output disabled and 5.5 V All -50 +50 A Output short circuit current 2/ 3/ IOSVCC= 5.5 V, VOUT= 0.5 V All -30 -90 mA Power supply current 4/ ICCVCC= 5.5 V, IOUT= 0 mA, VIN= 0 V and 5.5 V f = 1.0 MH

41、z All 220 mA Input capacitance 2/ CINSee 4.4.1e 4 All 10 pF Output capacitance 2/ COUT4 All 12 pF Functional test See 4.4.1c 7,8A,8B All Input to combinatorial output 5/ 6/ tPDSee figures 3 and 4 (circuit A) 9, 10, 11 01 15 ns 02 12 Input to output through transparent input or output latch 5/ 6/ tPD

42、L01 22 ns 02 18 Input to output through transparent input or output latches 5/ 6/ tPDLL01 24 ns 02 20 Input to output enable 5/ 6/ (see figure 3 test waveforms) tEASee figures 3 and 4 (circuit B) 9, 10, 11 01 24 ns 02 19 Input to output disable 5/ 6/ (see figure 3 test waveforms) tER01 24 ns 02 19 S

43、ee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performan

44、ce characteristics - Continued. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgroups Device type Limits Unit Min Max Clock or Latch enable input high time 2/ 5/ tWHSee figures 3 and 4 (circuit A) 01 5 ns 02 4 Clock or latch enable input low time 2/ 5/ tWL

45、01 5 ns 02 4 Input register or latch set-up time 5/ tIS01 4 ns 02 3 Input register or latch hold time 5/ tIH01 4 ns 02 3 Input register clock or latch enable to combinatorial output 5/ tICO01 24 ns 02 19 Input register clock or latch enable to output through transparent output latch 5/ 6/ tICOL01 26

46、 ns 02 21 Clock or latch enable to output 5/ tCO01 10 ns 02 8 Register or latch data hold time 5/ tHAll 0 ns Set-up time from input to clock or latch enable 5/ tS01 10 ns 02 8 Set-up time from input through transparent latch to output register clock or latch enable 5/ 6/ tSL01 20 ns 02 15 See footno

47、tes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94684 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance charac

48、teristics - Continued. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgroups Device type Limits Unit Min Max Output clock or latch enable to output delay (through memory array) 5/ 6/ tCO2See figures 3 and 4 (circuit A) 9, 10, 11 01 24 ns 02 19 Output clock or latch enable to output clock or latch enable (through memory array) 5/ 6/ tSCS01 15 ns 02 12 Hold time for input through transparent latch from output reg