DLA SMD-5962-93189 REV D-2013 MICROCIRCUIT MEMORY CMOS 4K X 18 PARALLEL SYNCHRONOUS FIFO MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated boilerplate. Added flat package - glg 94-08-31 M. A. Frye B Changes in accordance with NOR 5962-R054-95. - glg 95-01-30 Michael A. Frye C Changes in accordance with NOR 5962-R172-95. - jb 95-08-22 Michael A. Frye D Updated drawing to reflect current

2、 MIL-PRF-38535 requirements. - glg 13-03-25 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC

3、N/A PREPARED BY Tuan Nguyen DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, CMOS, 4K X 18 PARALLEL SYNCHRONOU

4、S, FIFO, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93 06 15 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-93189 SHEET 1 OF 27 DSCC FORM 2233 APR 97 5962-E330-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

5、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93189 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space appli

6、cation (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 -

7、93189 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RH

8、A levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circ

9、uit function as follows: Clock cycle Device type Generic number 1/ Circuit function time (min) 01 4K X 18 CMOS parallel synchronous FIFO 50 ns 02 4K X 18 CMOS parallel synchronous FIFO 35 ns 03 4K X 18 CMOS parallel synchronous FIFO 25 ns 1.2.3 Device class designator. The device class designator is

10、 a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qua

11、lification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style X CMGA3-PN 68 2/ Pin grid array Y See figure 1 68 Flat package 1.2.5 Lead finish. The lead finish is as specified in

12、 MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Generic numbers are also listed on the Standard Microcircuit Drawing Source Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ 68 = the actual number of pins used, not the maxi

13、mum listed in MIL-HDBK-1835. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93189 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings.

14、3/ Terminal voltage with respect to ground . -0.5 V dc to +7.0 V dc DC output current . 50 mA Storage temperature range -65C to +150C Maximum power dissipation (PD) 1.25 W Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC): Case X . See MIL-STD-1835 Case Y . 1

15、0 C/W Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage (VCC) . +4.5 V dc to +5.5 V dc Supply voltage (GND) . 0 V Minimum high level input voltage (VIH) . 2.2 V dc minimum Maximum low level input voltage (VIL) . +0.8 V dc minimum 4/ Case operating temperature ran

16、ge (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the s

17、olicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTME

18、NT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philad

19、elphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC La

20、tch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cite

21、d herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum

22、 levels may degrade performance and affect reliability. 4/ -1.5 V undershoots are allowed for 10 ns once per cycle. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93189 DLA LAND AND MARITIME COLUMBUS, OHIO 4

23、3218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualifi

24、ed Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF

25、-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in

26、 accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be

27、 in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrica

28、l performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are described in table I.

29、 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has

30、the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accor

31、dance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to D

32、LA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A

33、shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent and

34、the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

35、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93189 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device typ

36、es Limits Unit Min Max Input leakage current ILI0.4 V VIH, 0.4 V the minimum limit, tFRL(max) = tCLK+ tSKEW2. When tSKEW2the minimum limit specified in Table I, tFRL(maximum) = tCLK+ tSKEW2. When tSKEW2 the minimum limit, tFRL(maximum) = either 2tCLK+ tSKEW2or tCLK+ tSKEW2. The latency timing applie

37、s only at the empty boundary ( EF = LOW). 7. The first word is always available one cycle after EF goes high. 8. PAE is offset = n. Number of data words written into FIFO already = n. 9. PAF offset = m. Number of data words written into FIFO already = 4096 m + 1. 10. Write to last physical location.

38、 11. Read from last physical location. FIGURE 5. Switching time waveforms - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93189 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SH

39、EET 25 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality

40、conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity

41、upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein, ex

42、cept interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional

43、 criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CINand COUT measurement) shall be measured only for the initial test and after any design or process chang

44、es which may affect capacitance. Sample size is 15 devices with no failures, and all input and output terminals tested. d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M,

45、 procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufactur

46、ers TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JESD 78 may be used for referen

47、ce. e. Subgroups 7 and 8 tests shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table IIA herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall

48、 be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,