DLA SMD-5962-93159 REV A-2005 MICROCIRCUIT DIGITAL HCMOS VLSI INTEGRATED MULTIPROTOCOL PROCESSOR MONOLITHIC SILICON《硅单片 超大规模集成化多协议处理器 高密度互补金属氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-93159 REV A-2005 MICROCIRCUIT DIGITAL HCMOS VLSI INTEGRATED MULTIPROTOCOL PROCESSOR MONOLITHIC SILICON《硅单片 超大规模集成化多协议处理器 高密度互补金属氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-93159 REV A-2005 MICROCIRCUIT DIGITAL HCMOS VLSI INTEGRATED MULTIPROTOCOL PROCESSOR MONOLITHIC SILICON《硅单片 超大规模集成化多协议处理器 高密度互补金属氧化物半导体数字微型电路》.pdf（45页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-10-11 Thomas M. Hess REV A A A A A A A A A A SHEET 35 36 37 38 39 40 41 42 43 44 REV A A A A A A A A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

2、 34 REV A A A A A A A A A A A A A A REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen CHECKED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 98-12-1

3、1 MICROCIRCUIT, DIGITAL, HCMOS, VLSI, INTEGRATED MULTIPROTOCOL PROCESSOR, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-93159 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL A SHEET 1 OF 44 DSCC FOR

4、M 2233 APR 97 5962-E435-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. Thi

5、s drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radi

6、ation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93159 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see

7、 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the a

8、ppropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 68302 Integrated multiprotocol processor 1.2.3 Device class designator. The device class designator is a

9、 single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and quali

10、fication to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA5-P132 132 Pin grid array Y See figure 1. 132 Ceramic leaded chip carrier, gullwing-lead 1.2.5 Lead finish. The l

11、ead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COL

12、UMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) -0.3 V to +7.0 V Input voltage range (VIN) -0.3 V to VCCStorage temperature range (TSTG) . -55C to +150C Lead temperature (soldering, 10 seconds). +300C Thermal resistanc

13、e, junction-to-ambient (JA): Case X . 33C/W Case Y . 46C/W Power dissipation at 16.67 MHz (PD) . 53 mA minimum to 64 mA maximum 2/ Power dissipation at 8.0 MHz (PD) . 26 mA minimum to 31 mA maximum 2/ Low power dissipation at 16.67 MHz (LPD) 36 mA maximum 3/ Lowest power dissipation at 16.67 MHz (LP

14、D) . 32 mA maximum 4/ Lowest power dissipation at 50.0 kHz (LPD). 1 mA maximum 5/ 1.4 Recommended operating conditions. 2/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc High level input voltage (VIH): Except EXTAL 2.0 V minimum EXTAL . 4.0 V minimum (NMSI1 in IDL mode) L1CLK, L1SY1, L1RXD, L1GR

15、VDD- 20% Low level input voltage (VIL): Except EXTAL 0.8 V maximum EXTAL . 0.6 V maximum (NMSI1 in IDL mode) L1CLK, L1SY1, L1RXD, L1GR 0.2VDDFrequency of operation 8 - 16.67 MHz Ambient operating temperature range (TA) -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent

16、 damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ The values shown are typical. The typical value varies as shown, based on how many IMP on-chip peripherals are enabled and the rate at which they are clocked. 3/ LPREC = 0, Divider = 2.

17、 4/ LPREC = 1, Divider = 1024. 5/ The stated frequency must be externally applied to EXTAL only after the IMP has been placed in the lowest power mode with LPREC = 1. The device core is not specified to operate at frequency but the rest of the IMP is. In this configuration, the user does not divide

18、the clock internally using the LPCD4-LPCD0 bits in the system control register. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A

19、SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in

20、 the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DE

21、PARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk,

22、700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulation

23、s unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modificat

24、ion in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions.

25、The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal conn

26、ections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagrams. The functional block diagrams shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postir

27、radiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirem

28、ents shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

29、 OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufa

30、cturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.

31、 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a c

32、ertificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MI

33、L-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the r

34、equirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8

35、 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSC

36、Cs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices cover

37、ed by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REV

38、ISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Test conditions -55C TA +125C 1/ +4.5 V VDD +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit High level output voltage VOHVDD= 5.0 V IOH= 400 A All 1, 2, 3 VDD-

39、 1.0 Low level output voltage, A1-A23, PB0-PB11, FC0-FC2, CS1- CS0 , IAC, AVEC , BG , RCLK1-RCLK3, TCLK1-TCLK3, RTS1-RTS3 , SDS2, PA12, RXD2, RXD3, CTS2 , CD2 , CD3 , DREQ VOL1VDD= 5.0 V IOL= 3.2 mA All 1, 2, 3 0.5 Low level output voltage, AS ,UDS , LDS , R/ W ,BERR , BGACK , BCLR , DTACK , DACK ,R

40、MC , D0-D15,RESET VOL2VDD= 5.0 V IOL= 5.3 mA All 1, 2, 3 0.5 Low level output voltage, TXD1, TXD2, TXD3 VOL3VDD= 5.0 V IOL= 7.0 mA All 1, 2, 3 0.5 Low level output voltage,BR , DONE , HALT (BR as output) VOL4VDD= 5.0 V IOL= 8.9 mA All 1, 2, 3 0.5 Low level output voltage, CLKO VOL5VDD= 5.0 V IOL= 3.

41、2 mA All 1, 2, 3 0.4 V Input leakage current IINVDD= 5.5 V All 1, 2, 3 20 Three-state leakage current ITSIVDD= 5.5 V, VIN= VDDAll 1, 2, 3 20 Open drain leakage current IODVDD= 5.5 V, VIN= VDDAll 1, 2, 3 20 A CLKO OCLK50 ISDN I/F (GCI mode) OGCI150 Output drive All other pins OALLAll 1, 2, 3 130 Inpu

42、t capacitance CINSee 4.4.1c All 4 15 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 D

43、SCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol or Test no. Test conditions -55C TA +125C 1/+4.5 V VDD +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit NMSI1 in IDL mode High level output voltage, L1TXD, SDS1, SDS2, L1R

44、Q VOH2VDD= 5.0 V IOH= 2.0 mA All 1, 2, 3 VDD- 0.5 V Low level output voltage, L1TXD, SDS1, SDS2, L1RQ VOL6VDD= 5.0 V IOH= 2.0 mA All 1, 2, 3 0.5 V Low level input current IILVIN= VSSAll 1, 2, 3 10 A High level input current IIHVIN= VDDAll 1, 2, 3 10 A Functional tests See 4.4.1b All 7, 8 Clock timin

45、g Clock period (EXTAL) 1 60 125 Clock pulse width (EXTAL) 2,3 27 62.5 Clock rise and fall time (EXTAL) 4,5 5 EXTAL to CLKO delay 2/ 3/ 5A See figure 4 All 9, 10, 11 2 18 ns IMP bus master cycles Clock high to FC, address valid 6 45 Clock high to address, data bus high impedance (maximum) 7 50 Clock

46、high to address, FC invalid (minimum) 8 0 Clock high to AS ,DS asserted 4/ 9 3 30 Address, FC valid to AS , DS asserted (read)/ AS asserted (write) 5/ 11 15 Clock low to AS ,DS negated 4/ 12 30 AS ,DS negated to address, FC invalid 5/ 13 15 AS (andDS read) width asserted 5/ 14 120 DS width asserted,

47、 write 5/ 14A 60 AS ,DS width negated 5/ 15 See figure 4 All 9, 10, 11 60 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-93159 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

48、43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Test no. Test conditions -55C TA +125C 1/+4.5 V VDD +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit IMP bus master cycles Continued Clock high to control bus high impedance 16 50 AS ,DS negated to R/ W invalid 5/ 17 15 Clock high to R/ W high 4/ 18 30 Clock high to R/ W low 4/ 20 AS asserted to R/ W low (write) 5/ 9/ 20A 10 Address FC valid to R/ W low (write) 5/ 21 15 R/ W low toDS asserted (w