DLA SMD-5962-92024 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS 16-BIT D-TYPE TRANSPARENT LATCH WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

《DLA SMD-5962-92024 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS 16-BIT D-TYPE TRANSPARENT LATCH WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-92024 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS 16-BIT D-TYPE TRANSPARENT LATCH WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02 and case outline Y. Add delta limits to table III for device type 02. Update the boilerplate to remove classes B and S, to include radiation hardness assured requirements, and to reflect the changes in accordance with MIL-PRF-3

2、8535 requirements. Editorial changes throughout. TVN 04-05-12 Thomas M. Hess B Update radiation features in section 1.5. Add table IB and paragraphs 4.4.4.1 - 4.4.4.2. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-11-17 Thomas M. Hess REV SHET REV B B B B B B B SH

3、EET 15 16 17 18 19 20 21 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Wanda L. Meadows DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE

4、 BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Ricciuti APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 16-BIT D-TYPE TRANSPARENT LATCH WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-03-31

5、 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-92024 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E015-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92024 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVIS

6、ION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the P

7、art or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F 92024 01 V Y A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class d

8、esignatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-3

9、8535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACT16373 16-bit D-type transparent latc

10、h with three-state outputs, TTL compatible inputs 02 54ACT16373 16-bit D-type transparent latch with three-state outputs, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requir

11、ements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL

12、-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDFP1-F48 48 Flat packY See figure 1 48 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSN

13、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92024 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc

14、 to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc DC input clamp diode current (IIK) (VIN 0 V, VIN VCC) 20 mA DC output clamp diode current (IOK) (VOUT 0 V, VOUT VCC) . 50 mA DC output current (IOUT) (VOUT= 0 to VCC) (p

15、er output) 50 mA DC VCCor GND current (ICC, IGND) . 400 mA 4/ Maximum power dissipation (PD) . 500 mW Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X . See MIL-STD-1835 Case outline Y . 22C/W Ju

16、nction temperature (TJ) 175C 5/ 1.4 Recommended operating conditions. 2/ 3/ 6/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) . 0.0 V dc to VCCMinimum high level input voltage (VIH) . 2.0 V Maximum low level input voltage (VIL)

17、0.8 V Maximum high level output current (IOH) -24 mA Maximum low level output current (IOL) 24 mA Maximum Input rise or fall time rate (t/v): (10% to 90% of VIN, 90% to 10% of VIN) 10 ns/V Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features. Device type 02: Maximum total dos

18、e available (dose rate = 50 300 rads (Si)/s) 300 krads (Si) Single Event Latchup (SEL) see 4.4.4.2 93 MeV-cm2/mg 7/ Single Event or Single Event Upset (SEU) see 4.4.4.2 93 MeV-cm2/mg 7/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

19、maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For packages with multiple VCCa

20、nd GND pins, this value represents the maximum total current flowing into or out of all VCCor GND pins. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ Unused or floating inputs s

21、hould be held high or low. 7/ Limits obtained during technology characterization/qualification, guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

22、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92024 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handboo

23、ks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF D

24、EFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents ar

25、e available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless

26、 otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices. JEDEC Standard No. 78 - IC Latch-Up Test. (

27、Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the t

28、ext of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38

29、535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A

30、 for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.

31、2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

32、DRAWING SIZE A 5962-92024 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4. 3.2.5 Ground bounce waveforms and t

33、est circuit. The ground bounce waveforms and test circuit shall be as specified on figure 5. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 6. 3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by

34、 the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and

35、 postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table

36、 IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the dev

37、ice. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mar

38、k for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

39、 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of complianc

40、e submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A a

41、nd herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M

42、. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land a

43、nd Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M dev

44、ices covered by this drawing shall be in microcircuit group number 38 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92024 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

45、ISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type and device class VCCGroup A subgroups Limits 4/ Unit Min Max High leve

46、l output voltage 3006 VOHFor all inputs affecting output under test VIH= 2.0 V or 0.8 V For all other inputs VIN= VCCor GND IOH= -50 A All All 4.5 V 1, 2, 3 4.4 V 5.5 V 1, 2, 3 5.4 IOH= -24 mA 01 All 4.5 V 1 3.94 2, 3 3.7 5.5 V 1 4.94 2, 3 4.7 02 All 4.5 V 1, 2, 3 3.7 5.5 V 1, 2, 3 4.7 IOH= -50 mA 5

47、/ All All 5.5 V 1, 2, 3 3.85 Low level output voltage 3007 VOLFor all inputs affecting output under test VIH= 2.0 V or 0.8 V For all other inputs VIN= VCCor GND IOL= 50 A All All 4.5 V 1, 2, 3 0.1 V 5.5 V 1, 2, 3 0.1 IOL= 24 mA All Q, V 4.5 V 1, 3 0.36 2 0.50 All M 1 0.36 2, 3 0.50 All Q, V 5.5 V 1,

48、 3 0.36 2 0.50 All M 1 0.36 2, 3 0.50 IOL= 50 mA 5/ All All 5.5 V 1, 2, 3 1.65 Positive input clamp voltage 3022 VIC+For input under test, IIN= 1.0 mA All Q, V 0.0 V 1 0.4 1.5 V Negative input clamp voltage 3022 VIC-For input under test, IIN= -1.0 mA All Q, V Open 1 -0.4 -1.5 V Input current high 30

49、10 IIHFor input under test, VIN= VCCFor all other inputs VIN= VCCor GND All Q, V 5.5 V 1 0.1 A 2 1.0 All M 1 0.1 2, 3 1.0 Input current low 3009 IILFor input under test, VIN= GND For all other inputs VIN= VCCor GND All Q, V 5.5 V 1 -0.1 A 2 -1.0 All M 1 -0.1 2, 3 -1.0 See footnotes at end of table. Provided by IHSNot