DLA SMD-5962-91722 REV E-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS 4-BIT PRESETTABLE BINARY COUNTER ASYNCHRONOUS RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R410-97. 97-08-11 Monica L. Poelking B Add Radiation Hardness Assurance limits. Editorial changes throughout. jak 98-04-20 Monica L. Poelking C Add device type 02. Add case outlines X and Z. Add radiation featu
2、res to device type 01. Add Vendor CAGE Code F8859. Update boilerplate to MIL-PRF-38535 requirements. LTG 02-07-18 Thomas M. Hess D Change lead temperature for case outline X in 1.3. Add radiation features to 1.5 for device type 02. Update the boilerplate to include radiation hardness assured require
3、ments for device type 02. Editorial changes throughout. jak 04-12-01 Thomas M. Hess E Update radiation features in section 1.5. Add table IB and paragraphs 4.4.4.1 - 4.4.4.2. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-11-17 Thomas M. Hess REV SHET REV E E E E E
4、 E E E E SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS A
5、VAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Ricciuti APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 4-BIT PRESETTABLE BINARY COUNTER, ASYNCHRONOUS RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL D
6、ATE 92-12-23 REVISION LEVEL E SIZE A CAGE CODE 67268 5962-91722 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E072-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91722 DLA LAND AND MARITIME COLUMBUS, OHIO 4321
7、8-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflec
8、ted in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F 91722 01 V E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)De
9、vice class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet t
10、he MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 1/ 54ACT161 4-bit presettable
11、 binary counter, asynchronous reset, TTL compatible inputs 02 54ACT161 4-bit presettable binary counter, asynchronous reset, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device req
12、uirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in
13、MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack X CDFP4-F16 16 Flat packZ GDFP1-G16 16 Flat pack with gullwing 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The
14、lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Due to internal noise problems, device type 01 does not meet the minimum VIHthreshold limit that is characteristic of this technology family. Provided by IHSNot for ResaleNo re
15、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91722 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Input v
16、oltage range . -0.5 V dc to VCC + 0.5 V dc 2/ Output voltage range -0.5 V dc to VCC+ 0.5 V dc 2/ DC input diode current (IIK) (-0.5 V VIN VCC+ 0.5 V) 20 mA DC output diode current (IOK) (-0.5 V VOUT VCC+ 0.5 V) 20 mA DC output current (IOUT) (per output pin) 50 mA DC VCCor GND current (ICC, IGND) (p
17、er pin) . 250 mA 3/ Maximum power dissipation (PD) . 500 mW Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds): Case outline X . +260C All other case outlines except case X +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (T
18、J) +175C 4/ 1.4 Recommended operating conditions. 2/ 5/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage range (VOUT) . +0.0 V dc to VCCMaximum low level input voltage (VIL) 0.8 V dc Minimum high level input voltage (VIH): Device type 01 3.0
19、V dc 6/ Device type 02 2.0 V dc Case operating temperature range (TC) . -55C to +125C Input edge rate (v/t) maximum (from VIN= 0.8 V to 2.0 V, 2.0 V to 0.8 V) . 125 mV/ns Maximum high level output current (IOH) . -24 mA Maximum low level output current (IOL) . +24 mA 1.5 Radiation features. Device t
20、ype 01: Maximum total dose available (dose rate = 50 300 rads (Si)/s) 100 Krads (Si) Single Event Latch-up (SEL) occurs at LET (see 4.4.4.2) . 100 MeV-cm2/mg 7/ Device type 02: Maximum total dose available (dose rate = 50 300 rads (Si)/s) 300 krads (Si) Single Event Latchup (SEL) occurs at LET (see
21、4.4.4.2) . 93 MeV-cm2/mg 7/ Single Event Upset (SEU) occurs at LET (see 4.4.4.2) 93 MeV-cm2/mg 7/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted
22、, all voltages are referenced to GND. 3/ For packages with multiple VCCand GND pins, this value represents the maximum total current flowing into or out of all VCCand GND pins. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in a
23、ccordance with method 5004 of MIL-STD-883. 5/ Unless otherwise specified, the values listed above shall apply over the full VCCand TCrecommended operating range. 6/ For dynamic operation, a VIHlevel between 2.0 and 3.0 V may be recognized by this device as a high logic level input. For static operat
24、ion, a VIH 2.0 V will be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system. 7/ Limits obtained during technology characterization/qualification, guaranteed by design or process, but not production tested unless specified by th
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