DLA SMD-5962-91692 REV A-2002 MICROCIRCUIT LINEAR CMOS 16-BIT 20 KHZ A D CONVERTER MONOLITHIC SILICON《硅单块 交直流转换器 20 KHZ16比特互补金属氧化物半导体 直线式微型电路》.pdf

《DLA SMD-5962-91692 REV A-2002 MICROCIRCUIT LINEAR CMOS 16-BIT 20 KHZ A D CONVERTER MONOLITHIC SILICON《硅单块 交直流转换器 20 KHZ16比特互补金属氧化物半导体 直线式微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-91692 REV A-2002 MICROCIRCUIT LINEAR CMOS 16-BIT 20 KHZ A D CONVERTER MONOLITHIC SILICON《硅单块 交直流转换器 20 KHZ16比特互补金属氧化物半导体 直线式微型电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - lgt 02-04-18 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DEFENSE SUPPLY CENTER CO

2、LUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Sandra Rooney COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, CMOS, 16-BIT, 20 KHz, A/D CONVERTER, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF D

3、EFENSE DRAWING APPROVAL DATE 92-12-16 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91692 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E355-02 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted wit

4、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91692 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class

5、es Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the

6、 following example: 5962 - 91692 01 M X X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the M

7、IL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device

8、type(s) identify the circuit function as follows: Device type Generic number Circuit function Linearity error 01 SEI5102A-S 16-bit, 20 kHz analog to digital converter 3.0 LSB 02 SEI5102A-T 16-bit, 20 kHz analog to digital converter 2.0 LSB 1.2.3 Device class designator. The device class designator i

9、s a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qu

10、alification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead fin

11、ish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91692 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

12、OHIO 43216-5000 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Positive digital supply (+VD) voltage range. -0.3 V dc to +6.0 V dc 3/ Negative digital supply (-VD) voltage range +0.3 V dc to -6.0 V dc Positive analog supply (+VA) voltage range -0.3 V dc to +6.0 V

13、dc Negative analog supply (-VA) voltage range. +0.3 V dc to -6.0 V dc Input current, any pin except supplies 10 mA 4/ Analog input voltage (AIN and VREF pins). (-VA) 0.3 V dc to (+VA) + 0.3 V dc Digital input voltage -0.3 V dc to (+VA) + 0.3 V dc Storage temperature range. -65C to +150C Lead tempera

14、ture (soldering, 10 seconds). +260C Junction temperature (TJ) . +160C Power dissipation (PD) 72 mW Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) Case J. 40C/W Case 3. 60C/W 1.4 Recommended operating conditions. 1/ Ambient operating temperat

15、ure range (TA). -55C to +125C Positive digital supply voltage (+VD) . +4.50 V dc to +VANegative digital supply voltage (-VD). -4.50 V dc to -5.50 V dc Positive analog supply voltage (+VA) +4.50 V dc to +5.50 V dc Negative analog supply voltage (-VA) . -4.50 V dc to -5.50 V dc Analog reference voltag

16、e (VREF). +2.50 V dc to (+VA) -0.5 V dc Analog input voltage range: Unipolar. AGND V dc to VREF Bipolar. -VREFto VREF2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifi

17、ed herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, M

18、anufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. 1/ All voltages referenced to AGND and DGND tied together. 2/ Stresses above the absolute maximum rating ma

19、y cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ In addition, +VDmust not be greater than (+VA) + 0.3 V dc. 4/ Transient currents of up to 100 mA will not cause latch-up. Provided by IHSNot for ResaleNo reproduction o

20、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91692 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-

21、780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict betw

22、een the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirement

23、s for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements fo

24、r device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes

25、Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on f

26、igure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range.

27、3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be mark

28、ed as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device cl

29、asses Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark

30、for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For dev

31、ice class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm t

32、hat the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PR

33、F-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91692 DEFENSE SUPPLY CENT

34、ER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MI

35、L-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the optio

36、n of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A). 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and ins

37、pection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in ac

38、cordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with metho

39、d 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision leve

40、l control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA= +125C, minimum. b. Interim and final elect

41、rical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535

42、. The burn-in test circuit shall be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs,

43、outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device cl

44、ass Q shall be as specified in MIL-PRF-38535, appendix B. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91692 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 6 DSCC FORM 2234

45、 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA+125C unless otherwise specified Group A subgroups Device type 1/ Limits Unit Min Max Resolution for which no missing codes is guaranteed RES 2/ 1, 2, 3 All 16 Bits Integral linearity error INL 2/ 1, 2, 3 01 3.0 L

46、SB 02 2.0 Full-scale error FSE 2/ 1, 2, 3 01 5.0 LSB 02 3.0 Full-scale error drift FSE/t 2/ 3/ 4/ 2, 3 All 4.0 LSB Unipolar offset error VOFF 2/ 1, 2, 3 01 5.0 LSB 02 3.0 Unipolar offset error drift VOFF/t 2/ 3/ 4/ 2, 3 All 4.0 LSB Bipolar offset error BOFF 2/ 1, 2, 3 01 5.0 LSB 02 3.0 Bipolar offse

47、t error drift BOFF/t 2/ 3/ 4/ 2, 3 All 4.0 LSB Bipolar negative full-scale error BNFSE 2/ 1, 2, 3 01 5.0 LSB 02 3.0 Bipolar negative full-scale error drift BNFSE/t 2/ 3/ 4/ 2, 3 All 4.0 LSB Digital input voltage VIH5/ 6/ 7/ 1, 2, 3 All 2.0 V VIL0.8 Digital input current IIN5/ 6/ 1, 2, 3 All 10 A Dig

48、ital output voltage VOL5/ 6/ Logic “0”, ISINK= -1.6 mA 1, 2, 3 All 0.4 V VOH5/ 6/ Logic “1”, ISOURCE= 100 A +VD -1.0 Positive analog supply current IA+ 2/ 6/ 8/ +VA= 5.5 V dc 1, 2, 3 All 3.5 mA Negative analog supply current IA- 2/ 6/ 8/ -VA= -5.5 V dc 1, 2, 3 All -3.5 mA Positive digital supply cur

49、rent ID+ 2/ 6/ 8/ +VD= 5.5 V dc 1, 2, 3 All 3.5 mA Negative digital supply current ID- 2/ 6/ 8/ -VD= -5.5 V dc 1, 2, 3 All -2.5 mA Analog input capacitance in fine charge mode CIN2/ 3/ Unipolar mode 4 All 425 pF / 3/ Bipolar mode 265 See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or ne