DLA SMD-5962-91566 REV C-1996 MICROCIRCUIT DIGITAL CMOS SINGLE CHIP 8-BIT MICROCONTROLLER MONOLITHIC SILICON《硅单块 互补金属氧化物半导体单一芯片8比特微型控制器 数字微型电路》.pdf
《DLA SMD-5962-91566 REV C-1996 MICROCIRCUIT DIGITAL CMOS SINGLE CHIP 8-BIT MICROCONTROLLER MONOLITHIC SILICON《硅单块 互补金属氧化物半导体单一芯片8比特微型控制器 数字微型电路》.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-91566 REV C-1996 MICROCIRCUIT DIGITAL CMOS SINGLE CHIP 8-BIT MICROCONTROLLER MONOLITHIC SILICON《硅单块 互补金属氧化物半导体单一芯片8比特微型控制器 数字微型电路》.pdf(19页珍藏版)》请在麦多课文档分享上搜索。
1、= b 009345b 3T3 I PREPAREDBY Tim Noh CHECKED ay Tim Noh REV STrinJS OF SHEETS DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I PMIC NA 91 -0829 , REVISION LEVEL C STANDARD MICROCIRCUIT DRAWING 5962-91 566 SIZE CAGE CODE A 67268 THIS DRAWING IS AVAILABLE FOR USE BY AU DEPARTMENTS AND AGENCIES O
2、F THE DEPARTMENT OF DEFENSE AMSC NIA THE ORIGINAL FIRST PAGE OF MIS DRAWING HAS BEEN REPLACED. APPROVED BY D. M. cod MICROCIRCUIT, DIGITAL, CMOS SINGLE CHIP 8-81T MICROCONTROUER, MONOUTHIC SILICON I I SHEET 1 OF 18 DESC FORM 193 JUL 94 DlCTRi8UTION STATEMENT A. Approved for public release; distribut
3、ion is unlimited. 5962- port O = Vcc; X2, X1 = no connect; RST = Vss. Guaranteed to the limits specified, if mt tested. u I XgC= no connect, RST = Vcc. ICs uill be slightly higher if a crysta ts ud. when idle / X1 driven uith tc.ciir tCH is mesce. srt RSf = I s. = 5 ns, is measured with al? output p
4、ins diocLted; X1 driven with tCLCH, tCHCL ECss, x2 = no cmect, RST = v .) - to start cop plus 24tCLCL. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-m 9999996 0093463 533 m STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHI
5、O 65644 Device typt A 5962-91566 REVISION LEVEL SHEET C a Casa outline Terminal nrmbcr 1 2 3 4 5 6 7 8 9 10 11 12 13 11 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Al 1 L. x I 3 Terminal syrnbol P3. VA4 P3.3/A3 P3.2/AZ/AlO Pf .l/Al /A9 P3.Q/Ai/A8 PO. 2/V PO. 1 /sooo Pl.l/Dl P1 .zmr P1.3/D3 PU P1.51 i
6、N T 0/05 IC P1.6/1WT1/06 Pl .7/T0/07 P3.71 A7 P3.6/A6 P3.S/AS yr “cc _- ._ i FIGURE 1. -. i SIZE I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-= b 0093464 47T SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY
7、 CENTER DAYTON, OHIO 45444 REVISION LEVEL C I I “d 3 I I I I I I I I 1 I 5962-91566 SHEET 9 I I I I I 1- RST CONTROL ro I 1 I OSCILLATOR COR1 1 P2 .O-PZ. t FIGURE 2. Block diaurm. I I I 1 I I I I t I I I I I I I I I I I I I I I I I I I l I l I 1 I 1 Provided by IHSNot for ResaleNo reproduction or ne
8、tworking permitted without license from IHS-,-,-9999996 0091465 306 VCC -0.s 0.45 v EXTERNAL CLOCK ORIVE WAVEFORH VtC -0.5 0.2 vcc 4.9 0.2 vcc -0.1 0.45 v AC TESTING INPUT AND OUTPUT wviVEFoRn FIOURE 3. ma uavefornpg. STANDARD 5962-91 566 MICROC1RCUiT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON
9、, OHIO 45444 REVISION LEVEL I 1 I OESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-9999996 0093466 242 W MICROCIRCUIT DRAWNG DEFENSE ELECTRONICS SUPPLY CEMER DAYTON, OHIO 45444 4. QUALITY ASSURANCE PROVISIONS 4.1 and inswct ion.
10、For device classes N, a, and V, sanpling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Hanagant (an) plan. The modification in the H plan shall not affect the form, fit, or function as describad herein. For device class H, semp
11、ling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. conducted on all devices prior to qualification ad technology confonnnnce inspection- shall be in accordance with method 5004 of MIL-STO-883, and shall be conducted on all devices prior to quality conformance inspe
12、ction. 6.2 Screenins . . For device classes N, 9, and Y, screening shall be in accordance with MIL-PRF-38535, d shall bc For device class H, screening 4.2.1 Additional criteria for device class M. a. urn-in test, mathod 1015 of MIL-STO-=. (1) Test condition A, 8, C, or O. The test circuit shall be m
13、aintained by the manufacturer der docunmt revision level control an shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and pauar dissipation, as applicable, in accordance with the intent specified in test method 10
14、15 of UIL-STD-883. (2) TA = +12SmC, minim. b. c. Interim and final electrical test paremeters shalt be as specified in table It herein. A data retention stress test shall be includc as part of the screening procedure and shall consist of the follouing steps: SHEET li REVISION LEVEL C (1) Program gre
15、ater than 95 percent of the bit locations, including the slouest progrriwiing cell (see 3.11.21. The remining cells shatl provide a norst case spccd pattern. STANDARD A I (2) Bake, urbiassd, for 72 hwrs at 140.C to screen for data retention lifetime. (3) Perform a margin test using Vm = 5.9 V at 2S.
16、C using loose timing (i.e., TACC 1 CS). (4) Perform dynamic burn-in (see 4.2.la). (5) Margin at Vm = 5.9 V. (6) Perform electrical tests (see 4.2). (7) Erase (see 3.11.11, except devices subniitted for grorps A, E, C, and O testing. (81 Verify erasure (see 3.11.3). test method (1) Program at +ZT, 10
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