DLA SMD-5962-91542 REV E-2006 MICROCIRCUIT DIGITAL CMOS 8-BIT EPROM MICROCONTROLLER MONOLITHIC SILICON《硅单块 8比特可擦可编程序只读存储器微控制器 互补金属氧化物半导体 数字微型电路》.pdf

《DLA SMD-5962-91542 REV E-2006 MICROCIRCUIT DIGITAL CMOS 8-BIT EPROM MICROCONTROLLER MONOLITHIC SILICON《硅单块 8比特可擦可编程序只读存储器微控制器 互补金属氧化物半导体 数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-91542 REV E-2006 MICROCIRCUIT DIGITAL CMOS 8-BIT EPROM MICROCONTROLLER MONOLITHIC SILICON《硅单块 8比特可擦可编程序只读存储器微控制器 互补金属氧化物半导体 数字微型电路》.pdf（27页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Paragraph 1.2.4, modify case outline letter from Q to X. Figure 1, modify case outline letter from Q to X. 91-11-07 M. Poelking B Figure 3, IBF flag output waveforms, modify OBF (AFLAG) to read: IBF (BFLAG); add case outline M. Editorial changes

2、throughout. 92-09-28 M. L. Poelking C Changes in accordance with NOR 5962-R172-93. 93-06-07 Monica L. Poelking D Changes in accordance with NOR 5962-R101-96. 96-04-24 Monica L. Poelking E Update boilerplate to MIL-PRF-38535 requirements. - CFS 06-06-14 Thomas M. Hess REV SHET REV E E E E E E E E E E

3、 E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED Tim H. Noh DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil

4、THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, CMOS, 8-BIT EPROM AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-03-07 MICROCONTROLLER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-91542 SHEET

5、1 OF 26 DSCC FORM 2233 APR 97 5962-E396-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOP

6、E 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available,

7、a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91542 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (se

8、e 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are ma

9、rked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 87C451 CMOS 8-bit EPROM microcontroller 1.2.3 Device class designator. The device class d

10、esignator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certifica

11、tion and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style M GQCC1-J68 68 “J” lead chip carrier X CDIP1-T64 64 Dual-in-line 1.2.5 Lead finish. The lead finish is as

12、 specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321

13、8-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCCto VSS) -0.5 V dc to +6.5 V dc Voltage (any pin) to VSS(except VPP) . -0.5 V dc to VCC+ 0.5 V dc Voltage on VPP. -0.5 V dc to +13.0 V dc Storage temperature range -65C to +150C Maximum pow

14、er dissipation (PD) 200 mW Lead temperature (soldering, 5 seconds). +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage: All inputs except EA . 0.2VCC 0.25 V dc EA 0

15、.2VCC 0.45 V dc Minimum high level input voltage: All inputs except XTAL1, RST 0.2VCC+ 1.1 V dc XTAL1, RST. 0.7VCC+ 0.2 V dc Case operating temperature range (TC) . -55C to +125C Oscillator frequency . 3.5 MHz to 12 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.

16、The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufa

17、cturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard M

18、icrocircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conf

19、lict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause per

20、manent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUM

21、BUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM)

22、plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and ph

23、ysical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Termina

24、l connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 3. 3.3 Electrical performance char

25、acteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The elect

26、rical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entir

27、e SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for

28、device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appen

29、dix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a man

30、ufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the

31、requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be p

32、rovided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Veri

33、fication and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcirc

34、uit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59

35、62-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. See footnotes at end of table. Limits Test Symbol Conditions 1/ -55C 1 s). (4) Perform dynamic burn-in (see 4.2.1a). (5) Margin at Vm= +5.

36、9 V. (6) Perform electrical tests (see 4.2). (7) Erase (see 3.11.1), except devices submitted for groups A, B, C, and D testing. (8) Verify erasure (see 3.11.3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596

37、2-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 19 DSCC FORM 2234 APR 97 Margin test method B (1) Program at 25C 100 percent of the bits. (2) Bake, unbiased for 24 hours at +250C. (3) Perform margin test at Vm= +5.9 V. (4) Erase (see 3.11.1). (5) Perform inter

38、im electrical tests in accordance with table II. (6) Program 100 percent of the bits and verify (see 3.11.2). (7) Perform burn-in (see 4.2.1a). (8) One-hundred percent test at 25C (group A, subgroups 1 and 7). Vm= 5.9 V with loose timing, apply PDA. (9) Perform remaining final electrical subgroups a

39、nd group A testing. (10) Erase, devices may be submitted for groups B, C, and D at this time. (11) Verify erasure (see 3.11.3). Steps 1 through 4 are performed at wafer level. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or

40、approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be

41、 made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as sp

42、ecified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance wit

43、h MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including

44、groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and her

45、ein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91542 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 20

46、 DSCC FORM 2234 APR 97 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroup 4 (CI/O) shall be measured only for the initial test and after process or design changes which may affect capacitance. A minimum sample size of five devices with zero rejects shall be requ

47、ired. c. All devices selected for testing shall have the EPROM programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified (except devices submitted for groups C and D testing). d. For device class M, subgroups 7 and 8 tests shall c

48、onsist of verifying the EPROM pattern specified and the instruction set. The instruction set forms a part of the vendors test tape and shall be maintained and available from the approved source of supply. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the

49、device. TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Subgroups (in accordance with MIL-PRF-38535, table III) Device class M Device class Q Device class V Interim electrical parameters (see 4.2) - 1, 7 1, 7 Final electrical parameters (see 4.