DLA SMD-5962-90594 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS 16K X 4 SRAM WITH SEPARATE I O and TRANSPARENT WRITE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R188-95. 95-08-25 M. A. Frye B Updated boilerplate as part of 5 year review. ksr 08-11-07 Robert M. Heber THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV B B SHET 15 16 REV STATUS REV B

2、B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeffery D. Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY

3、Michael A. Frye DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-12-04 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 16K X 4 SRAM WITH SEPARATE I/O and TRANSPARENT WRITE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90594 SHEET 1 OF 16 DSCC FORM 2233

4、APR 97 5962-E025-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawi

5、ng describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962- 90594 01 X A | | | | | | | | | | | | Drawing number D

6、evice type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 1/ 16K X 4 SRAM separate I/O and transparent write 45 ns 02 1/ 16K X 4 SRAM sepa

7、rate I/O and transparent write 35 ns 03 1/ 16K X 4 SRAM separate I/O and transparent write 25 ns 04 1/ 16K X 4 SRAM separate I/O and transparent write 20 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Termin

8、als Package style X CDIP3-T28 or GDIP4-T28 28 dual-in-line package Y GDFP2-F28 28 flat package Z CQCC4-N28 28 rectangular leadless chip carrier package U CQCC3-N28 28 rectangular leadless chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolu

9、te maximum ratings. Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC voltage range applied to outputs in high Z state . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) 2/. -0.5 V dc to +7.0 V dc DC output current . 20 mA Maximum power dissipation (PD):. 1.0 W Lead tempera

10、ture (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . Case X, Y, Z, and U . See MIL-STD-1835 Junction Temperature (TJ) 3/. +150C Storage temperature range -65C to +150C Temperature under bias . -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.

11、5 V dc minimum to 5.5 V dc maximum Ground voltage (GND) (VSS). 0 V dc Input high voltage range (VIH). 2.2 V dc minimum Input low voltage range (VIL). 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approva

12、l Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ VILminimum = -3.0 V for pulse width less than 20 ns. 3/ Maximum junction temperature may be increased to +175C during burn-in and steady state life. Provided by IHSNot for ResaleNo reproduction or networking permitted

13、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards

14、, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DE

15、PARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these

16、 documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified he

17、rein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500

18、 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 O

19、rder of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1

20、 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manu

21、facturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may

22、make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design,

23、 construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Case outlines. The case outlines s

24、hall be in accordance with 1.2.2 herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Fun

25、ctional tests. Various functional tests used to test this device are contained in appendix A. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. Alternate test patterns shall be maintained under docum

26、ent revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see

27、 inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity. Samples may be pulled any t

28、ime after seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements sha

29、ll be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. F

30、or packages where marking the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PR

31、F-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be li

32、sted as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7

33、Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9

34、Verification and review. DSCC, DSCCs agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampl

35、ing and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-

36、in test (method 1015 of MIL-STD-883). (1) Test conditions D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, outputs, biases

37、, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at

38、 the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Elec

39、trical performance characteristics. Limits Test Symbol Conditions 1/ 2/ -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Min Max Unit Output high voltage VOHVCC= 4.5 V, IOH= -4.0 mA, VIN= VIHor VIL1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA V

40、IN= VIHor VIL1, 2, 3 All 0.4 V Input high voltage VIH 3/ 1, 2, 3 All 2.2 V Input low voltage VIL 3/ 1, 2, 3 All 0.8 V Input leakage current IIXVIN= 5.5 V to GND 1, 2, 3 All -10 10 A Output leakage current IOZVCC= 5.5 V VOUT= 5.5 V to GND 1, 2, 3 All -10 10 A 01,02 140 03 155 Operating supply current

41、 ICC1VCC= 5.5 V, IOUT= 0 mA CE = VIL, f = fMAX4/ 1, 2, 3 04 175 mA 01,02 50 03 60 Standby power supply current, TTL ICC2VCC= 5.5 V, IOUT= 0 mA CE VIH, f = 0 4/ all other inputs VILor VIH1, 2, 3 04 70 mA 01-03 20 Standby power supply current, CMOS ICC3CE (VCC-0.2 V), VCC= 5.5 V, f = 0 4/ all other in

42、puts 0.2 V or (VCC-0.2 V) 1, 2, 3 04 25 mA Input capacitance CIN 5/ VIN= 0.0 V, VCC= 5.0 V TA= +25C, f = 1 Mhz, (see 4.3.1c) 4 All 8 pF Output capacitance COUT 5/ VO= 0 V, VCC= 5.0 V TA= +25C, f = 1 Mhz, (see 4.3.1c) 4 All 8 pF Functional tests See 4.3.1d 7,8A,8B All See footnotes at the end of the

43、table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteris

44、tics - continued. Limits Test Symbol Conditions 1/ 2/ -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Min Max Unit 01 45 02 35 03 25 Read cycle time tAVAV9,10,11 04 20 ns 01 45 02 35 03 25 Address access time tAVQV9,10,11 04 20 ns Output hold from address chang

45、e tAVQX9,10,11 All 5 ns 01 45 02 35 03 25 Chip enable access time tELQV9,10,11 04 20 ns Chip enable to output active 5/ 6/ tELQX9,10,11 All 5 ns 01,02 15 03 10 Chip select to output inactive 5/ 6/ tEHQZ9,10,11 04 8 ns 01 25 02 20 03 12 Output enable to output valid tOLQV9,10,11 04 10 ns Output enabl

46、e to output active 5/ 6/ tOLQX9,10,11 All 3 ns 01,02 15 03 10 Output enable to output inactive 5/ 6/ tOHQZSee figures 3 and 4 9,10,11 04 8 ns See footnotes at the end of the table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

47、 DRAWING SIZE A 5962-90594 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Limits Test Symbol Conditions 1/ 2/ -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Min Max Unit Chip enable to power up 5/ tELPU9,10,11 All 0 ns 01 45 02 35 03 25 Chip enable to power down 5/ tEHPD9,10,11 04 20 ns 01 40 02 30 03 20 Write cycle time tAVAV9,10,11 04 20 ns 01 35 02 25 03 20 Chip enable to write end tELWH tELEH9,10,11 04 17 ns