DLA SMD-5962-90585 REV B-2010 MICROCIRCUIT DIGITAL BIPOLAR ADVANCE SCHOTTKY TTL MULTI-MODE BUFFERED LATCH INV (THREE-STATE) MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Corrections on table I. Editorial changes throughout. 92-04-06 Monica L. Poelking B Update drawing to current requirements. Editorial changes throughout. - gap 10-02-24 Charles F. Saffle The original first sheet of this drawing has been replaced.

2、 REV SHET REV SHET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Larry T. Gauder DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPART

3、MENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Tim H. Noh APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCE SCHOTTKY TTL, MULTI-MODE BUFFERED LATCH, INV. (THREE-STATE), MONOLITHIC SILICON DRAWING APPROVAL DATE 90-07-11 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268

4、 5962-90585 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E489-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2

5、234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-90585 01 K X Drawin

6、g number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54F432 Multi-mode buffered latch. inverting (three-state) 1.2.2 Case outline(s). The case o

7、utline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP4-T24 24 Dual-in-line package 3 CQCC1-N28 28 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in

8、 MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc minimum to +7.0 V dc maximum Input voltage range -0.5 v dc minimum to +7.0 V dc maximum Input current range -30 mA to +5.0 mA Voltage applied to output in high output state range -0.5 V to +VCCCurrent applied

9、to output in low output state . 40 mA Maximum power dissipation (PD) 1/ 385 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C Storage temperature -65C to +150C 1.4 Recommended operating conditions. Supply volt

10、age (VCC) 4.5 V dc minimum to 5.5 V dc maximum Minimum high-level input voltage (VIH) 2.0 V dc Maximum low-level input voltage (VIL) . 0.8 V dc Input clamp current -18 mA High level output current INT$ $ $ $ $. -1.0 mA Q0 to Q7 -3.0 mA Low-level output current 20 mA _ 1/ Must withstand the added PDd

11、ue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 Recommended o

12、perating conditions - Continued. Case operating temperature range (TC) . -55C to +125C Minimum setup time, Dn to S0$ $ $ $, S1, STB or M: TC= +25C 0 ns TC= -55C, +125C . 1.0 ns Minimum hold time, Dn to S0$ $ $ $, S1, STB or M: (H) TC= +25C 9.0 ns TC= -55C, +125C . 9.5 ns Minimum hold time, Dn to S0$

13、 $ $ $, S1, STB or M: (L) TC= +25C 8.0 ns TC= -55C, +125C . 9.5 ns Minimum pulse width, S0$ $ $ $, S1, or STB: TC= +25C 8.0 ns TC= -55C, +125C . 9.0 ns Minimum pulse width, MR$ $ $ $ $TC= +25C 8.0 ns TC= -55C, +125C . 9.0 ns Minimum recovery time TC= +25C 0 ns TC= -55C, +125C . 0 ns 2. APPLICABLE DO

14、CUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF D

15、EFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - L

16、ist of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order o

17、f precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for Re

18、saleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements sha

19、ll be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certificatio

20、n to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These mo

21、difications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dim

22、ensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Tru

23、th tables. The truth tables shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. Test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unl

24、ess otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests

25、 for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not f

26、easible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be r

27、eplaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.

28、6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as

29、required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquirin

30、g activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI

31、CROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min Max High lev

32、el output voltage VOHVCC= 4.5 V VIL= 0.8 V VIH= 2.0 V IOH= -1 mA 1, 2, 3 2.5 V IOH= -3 mA 2.4 V Low level output voltage VOLVCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V, IOL= 20 mA 1, 2, 3 0.5 V Input clamp voltage VIKVCC= 4.5 V, IIK= -18 mA 1, 2, 3 -1.2 V Input current at maximum input voltage IINVCC= 5.5 V,

33、 VIN= 7.0 V 1, 2, 3 100 A High level input current IIHVCC= 5.5 V, VIN= 2.7 V 1, 2, 3 20 A Low level input current IIL VCC= 5.5 V, VIN= 0.5 V 1, 2, 3 -0.6 mA Off-state output current, high level voltage applied IOZHVCC= 5.5 V, VO= 2.7 V 1, 2, 3 50 A Off-state output current, low level voltage applied

34、 IOZLVCC= 5.5 V, VO= 0.5 V 1, 2, 3 -50 A Short circuit output current 1/ IOSVCC= 5.5 V, VO= 0.0 V 1, 2, 3 -60 -150 mA Supply current ICCH VCC= 5.5 V 1, 2, 3 55 mA ICCL 70 ICCZ 65 Functional tests See 4.3.1c, VCC= 4.5 V, 5.5 V 7, 8 Propagation delay, Dn to Qn tPLH1RL= 500 CL= 50 pF See figure 4 VCC=

35、5.0 V 9 4.5 10.5 ns VCC= 4.5 V and 5.5 V 10,11 4.0 13.0 tPHL1VCC= 5.0 V 9 2.5 7.0 ns VCC= 4.5 V and 5.5 V 10,11 2.5 6.0 Propagation delay, S0$ $ $ $, S1, or STB to Qn tPLH2VCC= 5.0 V 9 8.5 17.0 ns VCC= 4.5 V and 5.5 V 10,11 8.0 24.0 tPHL2VCC= 5.0 V 9 6.0 13.0 ns VCC= 4.5 V and 5.5 V 10,11 5.5 14.0 S

36、ee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical

37、performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay, S0$ $ $ $or S1 to INT$ $ $ $ $tPLH3RL= 500 CL= 50 pF See figure 4 VCC= 5.0 V 9 3.0 9.5 ns VCC= 4.5 V and 5.5 V 10,11 2.5 10.5 tPHL3VCC= 5.

38、0 V 9 3.5 10.0 ns VCC= 4.5 V and 5.5 V 10,11 3.0 10.5 Propagation delay, MR$ $ $ $ $to Qn tPLH4VCC= 5.0 V 9 8.0 16.0 ns VCC= 4.5 V and 5.5 V 10,11 7.5 18.5 Propagation delay, STB to INT$ $ $ $ $tPHL4VCC= 5.0 V 9 7.0 13.5 ns VCC= 4.5 V and 5.5 V 10,11 6.5 14.5 Output enable time to high or low level

39、S0$ $ $ $or S1 to to Qn tPZH1VCC= 5.0 V 9 6.0 12.5 ns VCC= 4.5 V and 5.5 V 10, 11 5.5 15.5 tPZL1VCC= 5.0 V 9 6.0 14.0 ns VCC= 4.5 V and 5.5 V 10, 11 5.5 15.0 Output disable time from high or low level S0$ $ $ $or S1 to Qn tPHZ2VCC= 5.0 V 9 4.0 11.5 ns VCC= 4.5 V and 5.5 V 10, 11 3.5 12.5 tPLZ2VCC= 5

40、.0 V 9 6.0 15.0 ns VCC= 4.5 V and 5.5 V 10, 11 5.5 17.0 Output enable time to high or low level M to Qn tPZH3VCC= 5.0 V 9 5.0 11.0 ns VCC= 4.5 V and 5.5 V 10, 11 4.5 12.0 tPZL3VCC= 5.0 V 9 6.0 11.5 ns VCC= 4.5 V and 5.5 V 10, 11 5.5 13.0 Output disable time from high or low level M to Qn tPHZ4VCC= 5

41、.0 V 9 3.5 9.5 ns VCC= 4.5 V and 5.5 V 10, 11 3.0 10.5 tPLZ4VCC= 5.0 V 9 6.0 13.0 ns VCC= 4.5 V and 5.5 V 10, 11 5.5 15.0 1/ Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimi

42、ze internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOStests should be performed last. Prov

43、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Case outlines K and L 3 Terminal number Terminal conne

44、ctions 1 S0$ $ $ $NC 2 M S0$ $ $ $3 D0 M 4 Q0$ $ $ $D0 5 D1Q0$ $ $ $6 Q1$ $ $ $D1 7 D2Q1$ $ $ $8 Q2$ $ $ $NC 9 D3 D210 Q3$ $ $ $Q2$ $ $ $11 STB D312 GND Q3$ $ $ $13 S1 STB14 MR$ $ $ $ $GND 15 Q4$ $ $ $NC 16 D4 S1 17 Q5$ $ $ $MR$ $ $ $ $18 D5Q4$ $ $ $19 Q6$ $ $ $D4 20 D6Q5$ $ $ $21 Q7$ $ $ $D5 22 D7

45、NC23 INT$ $ $ $ $Q6$ $ $ $24 VCCD6 25 Q7$ $ $ $26 D727 INT$ $ $ $ $28 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 432

46、18-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Data latches function table. Inputs Data Data Operating MR$ $ $ $ $M S0$ $ $ $S1 STB In Out Mode L H H X X X H Clear L L L H L X H X L X L X X Z De-select X L H X X X Z H H H X X X Q0$ $ $ $Hold H L L H L X Q0$ $ $ $H H L H X L H Data Bus H H L

47、H X H L H L L H H L H Data Bus H L L H H H L H = High voltage level L = Low voltage level X = Irrelevant Z = High impedance Status flip-flop function table Inputs Output MR$ $ $ $ $S0$ $ $ $S1 STB INT$ $ $ $ $L H X X H L X L X H H X X L H L H X L H = High voltage level L = Low voltage level X = Irre

48、levant = High-to-low clock transition FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90585 DE