DLA SMD-5962-89545 REV B-2008 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY 8-BIT BIDIRECTIONAL BINARY COUNTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Revise for “QD” certification. New boilerplate. Editorial changes throughout. -ljs 00-02-24 Raymond Monnin B Update drawing to current requirements. Editorial changes throughout. - gap 08-06-06 Robert M. Heber The original first page of this draw

2、ing has been replaced. REV SHET REV B SHET 15 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A.

3、Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-03-13 MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, 8-BIT BIDIRECTIONAL BINARY COUNTER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A

4、CAGE CODE 67268 5962-89545 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E405-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEE

5、T 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-8954

6、5 01 R X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54F579 8-bit bidirectional binary counter, with three-state outputs 1.2.2 Ca

7、se outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line S GDFP2-F20 or GDFP3-F20 20 flat package 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish. The lead finish i

8、s as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc minimum to 7.0 V dc maximum Input voltage range . -0.5 V dc minimum to 7.0 V dc maximum Input current range -30 mA minimum to +5.0 mA maximum Voltage applied to output in high output state . -0.

9、5 V dc to + 5.5 V Current applied to output in low output state 40 mA Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1/ . 825 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C _ 1

10、/ Must withstand the added PDdue to short circuit-test, e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC

11、FORM 2234 APR 97 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) . 4.5 V dc minimum to 5.5 V dc maximum High level input voltage (VIH) . 2.0 V dc Low level input voltage (VIL) 0.8 V dc Case operating temperature range (TC) -55C to +125C Minimum setup time, I/Onto CP (tS(H), tS(L)

12、: TC= +25C 3.0 ns TC= -55C, +125C . 4.0 ns Minimum hold time, I/Onto CP (th(H), th(L): TC= +25C 0.0 ns TC= -55C, +125C . 0.0 ns Minimum setup time, PE , SR , or CS to CP, (tS(H): TC= +25C 9.5 ns TC= -55C, +125C . 11.0 ns Minimum setup time, PE , SR , or CS to CP, (tS(L): TC= +25C 9.5 ns TC= -55C, +1

13、25C . 13.0 ns Minimum hold time, PE , SR , or CS to CP, (tS(H), th(L): TC= +25C 0.0 ns TC= -55C, +125C . 0.0 ns Minimum setup time, CEP or CET to CP, (tS(H): TC= +25C 5.0 ns TC= -55C, +125C . 7.5 ns Minimum setup time, CEP or CET to CP, (tS(L): TC= +25C 9.0 ns TC= -55C, +125C . 11.5 ns Minimum setup

14、 time, CEP or CET to CP, (tS(H), th(L): TC= +25C 0.0 ns TC= -55C, +125C . 0.0 ns Minimum clock pulse width, (tW(H), tW(L): TC= +25C 4.5 ns TC= -55C, +125C . 6.0 ns Minimum MR pulse width, (tW(L): TC= +25C 3.0 ns TC= -55C, +125C . 3.0 ns Minimum recovery time, (tREC): TC= +25C 4.0 ns TC= -55C, +125C

15、. 5.0 ns _ 2/ See figure 4, waveform 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICA

16、BLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMEN

17、T OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-1

18、03 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Or

19、der of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1

20、Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manu

21、facturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may

22、make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow opt

23、ion is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the qualifying activity. 3.2 Design, construction, and physical dimensions. The design, construction, and phy

24、sical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as spec

25、ified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

26、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specifie

27、d in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance w

28、ith MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962

29、-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identif

30、y when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark. 3.6 Certificate of compliance. A certificate of compliance shall

31、be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38

32、535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be requir

33、ed for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer.

34、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. T

35、est Symbol Conditions -55C TC+125C Group A subgroups Limits Unit unless otherwise specified Min Max High level output voltage TC VOH1 VCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V, IOH= -1.0 mA 1, 2, 3 2.5 V IOH= -3.0 2.4 High level output voltage I/On VOH2 VCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V IOH= -1.0 1, 2, 3

36、2.5 V Low level output voltage VOL VCC= 4.5 V, IOL= 20 mA, VIL= 0.8 V, VIH= 2.0 V 1, 2, 3 0.50 V Input clamp voltage VIK VCC= 4.5 V, IIN= -18 mA 1, 2, 3 -1.2 V VCC= 5.5 V, VIN= 5.5 V I/On1, 2, 3 1.0 mA Input current at maximum input voltage IIH1 VCC= 5.5 V, VIN= 7.0 V All others 1, 2, 3 100 A High l

37、evel input current, except I/On IIH2 VCC= 5.5 V, VIN= 2.7 V 1, 2, 3 20 A Low level input current, except I/On IIL1 VCC= 5.5 V, VIN= 0.5 V 1, 2, 3 0.6 mA Off state current high level voltage applied to I/On IOZH VCC= 5.5 V, VIN= 2.7 V, VIH= 2.0 V 1, 2, 3 70 A Off state current low level voltage appli

38、ed to I/On IOZL VCC= 5.5 V, VIN= 0.5 V, VIH= 2.0 V 1, 2, 3 -600 A Short circuit output current IOS VCC= 5.5 V, VOUT= GND 1/ 1, 2, 3 -60 -150 mA Supply current (total) ICCHVCC= 5.5 V 1, 2, 3 135 mA ICCL1, 2, 3 145 CCZ1, 2, 3 150 Functional tests See 4.3.1c 7, 8 9 100 Maximum clock frequency fMAXSee w

39、aveform 1 2/ 10, 11 80 MHz Propagation delay, tPLH1 See Waveform 1 9 5.0 10.5 ns CP to I/On10, 11 4.5 23.0 tPHL19 5.0 10.5 VCC= 5.0 V, CL= 50 pF, RL= 500 See figure 4 10, 11 5.0 12.5 Propagation delay, tPLH2 See Waveform 1 9 5.5 10.0 ns CP to TC 10, 11 5.0 19.5 tPHL29 5.5 10.0 10, 11 5.0 12.0 See fo

40、otnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical perfo

41、rmance characteristics Continued. Test Symbol Conditions -55C TC+125C Group A subgroups Limits Unit unless otherwise specified Min Max Propagation delay, tPLH3 See Waveform 1 9 3.5 8.0 ns U/ D to TC 10, 11 3.5 12.5 tPHL39 4.5 8.0 VCC= 5.0 V, CL= 50 pF, RL= 500 See figure 4 10, 11 4.5 10.0 Propagatio

42、n delay, tPLH4 See Waveform 1 9 3.5 7.0 ns CET to TC 10, 11 3.5 9.5 tPHL49 3.5 8.0 10, 11 3.5 9.0 Propagation delay, tPHL5 See Waveform 2 9 5.0 9.0 ns MR to I/On 10, 11 5.0 11.0 9 3.0 7.5 tPHZ1 See Waveform 610, 11 3.0 10.0 ns 9 6.5 9.5 Output disable time from high to low level CS , PE , to I/OntPL

43、Z1 See Waveform 710, 11 5.5 12.0 ns 9 5.0 10.5 tPZH2 See Waveform 610, 11 3.5 12.5 ns 9 6.5 10.5 Output enable time to high to low level CS , PE , to I/OntPZL2 See Waveform 710, 11 5.5 13.0 ns 9 1.0 4.0 tPHZ3 See Waveform 610, 11 1.0 8.0 ns 9 2.5 7.0 Output disable time from high to low level OE to

44、I/OntPLZ3 See Waveform 710, 11 2.0 10.0 ns 9 4.0 8.5 tPZH4 See Waveform 610, 11 3.5 11.0 ns 9 5.0 9.5 Output enable time to high to low level OE to I/OntPZL4 See Waveform 710, 11 4.5 11.5 ns 1/ Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatu

45、s, sample-and-hold techniques, or both are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In

46、any sequence of parameter tests, IOStests should be performed last. 2/ This parameter is guaranteed but not tested to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEF

47、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Case outlines R and S 2 Terminal number Terminal symbol 1 CP CET2 I/O0 CEP3 I/O1 SR4 I/O2 MR5 I/O3 CP 6 GND I/O0 7 I/O4 I/O1 8 I/O5 I/O2 9 I/O6 I/O3 10 I/O7 GND 11 OEI/O4 12 CSI/O5 13 PEI/O6 14 U/ D

48、I/O7 15 TCOE16 VCC CS17 CETPE18 CEPU/ D 19 SRTC20 MRVCC FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89545 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 Inputs Operating mode MR SR CS PE CEP CET U/ D OE CP X X H X X X X X X I/O0to I/O7in high impedance ( PE disabled) X X L H X X X H X I/