DLA SMD-5962-88599-1988 MICROCIRCUITS DIGITAL CMOS TIMING CONTROL UNIT MONOLITHIC SILICON《硅单片时序控制组件互补型金属氧化物半导体数字微电路》.pdf
《DLA SMD-5962-88599-1988 MICROCIRCUITS DIGITAL CMOS TIMING CONTROL UNIT MONOLITHIC SILICON《硅单片时序控制组件互补型金属氧化物半导体数字微电路》.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-88599-1988 MICROCIRCUITS DIGITAL CMOS TIMING CONTROL UNIT MONOLITHIC SILICON《硅单片时序控制组件互补型金属氧化物半导体数字微电路》.pdf(18页珍藏版)》请在麦多课文档分享上搜索。
1、f LTR DESCRIPTION DATE (YR-W-M) APPROVED REV SHEET REV SHEFI REV STATUS OF SHEETS I I REV SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC NIA 16 17 18 STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE PREPAREDBY DEFENSE ELECTR
2、ONICS SUPPLY CENTER DAYTON, OHIO 45444 CHECKED BY 67268 15962-88599 REVISION LEVEL AMSC NIA I I SHEET 1 OF 18 DESC FORM 193 SEP 87 t U.S. GOYtWNl PRIHTING OfFlCE: I987 - 748.12916091 1 5962-E836 DISTRIBUTION STATEMENT A. Approved lor public release; distribution is unlimied. Provided by IHSNot for R
3、esaleNo reproduction or networking permitted without license from IHS-,-,-_ I I_I_ DESC-DWG-88597 57 W 9979975 0033045 4 a - 1. SCOPE 1.1 SCO e. This drawing describes device requirements for class B microcircuits in accordance rith 1.I I I I I 1 I I I i i i I 4 4 i 1 I I 1 I I I I I I 1 I I Lim i M
4、in 2.4 2.0 .8 4.275 -20 - i -I i i I -f -I i. 1 I I I I I I I I I I 7 I I I I I I ts I Unit Max I I I IV .8 I V I I 3.5 I v I 1.9 I v I I IV .525l V i I VA I I .5251 V I +20 I VA i .5251 V I I I I I I I I I I I I I I I I I I I 1,293 I 3.8 I IV IVOH II = Output high voltage All outputs except OUT STA
5、NDARDIZED SIZE I MILITAM DRAWING A 5962-88599 1 I DEFENSE ELECTRONICS SUPPLY CENTER REVWON LEVEL SHEET MUON, OHIO 45444 4 * U S. GWERNMENT PRINTING OFFCE 1987-549496 DESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-88577
6、 57 I 7777775 0013048 T CTANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON. OH0 45444 TABLE I. Electrical performance characteristics - Continued. I I I I I )subgroups- l I Vcc = 5.07 *5% I I Min I Max I I Il I I I unless otherwise specified I I I I I I Three-state leakage curren
7、t IIZH IForce 5.25 V on outputs, I 1,2,3 I I +20 I UA high Il MHz I I I I I Three-state leakage current /IL IForce 0.4 V on outputs, I NA 1 ow ll MHz I I I I I I I IFin = 10 MHz I I I I I I I I I I Test ISymbol I Condi ti ons 21 I Group A I Limits I Unit -55C 5 TC +125C I 1,2,3 I -20 I Supply curren
8、t IIcc IA11 outputs high I 1,2,3 I I 200 I mA 141 I 50 I PF 141 I 40 i PF I I I I I I i 40 i pF 141 I I I I C1 ock capacitance ICCLK I 21 I I Clock period ItCp PHI1 rising edge, to next I 9,10,11 I 100 I I ns I 7 IPHI1 rising edge I I I I I I 190 percent PHI1 rising edge, I 9,10,11 I 35 I 47 I ns o
9、90 percent PHI1 rising I I I I I I edge I I l I C1 ock high time I I 9 Ito 10 percent PHI1 rising I I I I I I edge I I I I I 10 I I I I I l I I I I I I I I I I I I I I I I 11 I input) I 1 12.5 V XIN falling edge I I I I I I I I I I input) I 2 12.5 V XIN rising edge I I I del ay I 3 to FCLK rising ed
10、ge I I I I I IC0 I Y I I I I Output capacitance Input capacitance ICI I Y ftCL$ It Clock low time ItcL1 Il0 percent PHI1 falling edge,( 9,10,11 I 43 I 60 I ns I Clock pulse width ItCLW1 (At 2.0 V on PHI1 (both edges11 9,10,11 I 40 I 52 I ns Clock pulse width Itc-wp IAt 2.0 V on PHI2 (both edges11 9,
11、10,11 I 40 I 52 I ns XIN high time (external ItXh 12.5 V XIN rising edge to I 9,iO,ii I 16 I I ns XIN low time (external Itxi 12.5 V XIN falling edge to 1 9,10,11 I 16 I I I I I I I I 3 I 29 I ns I I I I f 9y10,11 XIN to FCLK rising edge ltXFr 12.5 V XIN rising edge See footnotes at end of table. SI
12、ZE A 5962-88599 REVISION LEVEL SHEET 5 I I I - U.S.GOVERNMENTPRINTINGOFFffiE 1987-549098 DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-8577 57 - 7777775 0013047 1 TABLE 1. Electrical performance characteristics - Cont
13、inued. I Test I I Symbol I . Conditions 2/ I Group A I unless otherwise specified I I I I to FCLK fa1 1 i ng edge I I -55C 5 TC tl75“C VCC = 5-03 *5% i/ I -1 tXF to 30 percent or 70 percent of Vcc on all the CMOS input signals, and to 0.8 V or 2.0 V on all the TTL input signals, unless specifically
14、stated otherwise. g/ The capacitance measurements shall be made between the indicated termlnal and ground at a frequency of 1 MHz at TC of +25C. t0.1 V. The ac signal amplitude shall be less than 50 mV rms. I 35 I (slave) I I I I The dc bias of the measuring instrument shall be less than DUC FORM 19
15、3A SEP 87 f7 U.S.GOMRNMENT PRINTING OFFffiE 1987-549098 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-4577 57 7997795 0013051 T Device type O1 Case J 6 7 RSTO 8 PHIl II FIGURE 1. Terminal connections. SIZE A 5962-88599 STAN DARDI ZED MILIT
16、ARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OH10 45444 *us f;oviRhHIYTrRlflh(; nibirF: t987.7uI-ln-fmu DESC FORM 193A SEP 87 _-I- -CS= - -. _- _- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-8577 57 W 777777
17、5 0023052 2 W SIZE A STANDARDIZED 71-i I 1 5962-88599 ADS ODIN PER - DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL WAIT 4 WAIT2 WAIT I SHEET 9 FIGURE 2. Functional block diagram. f CLK PHI2 PHI1 CTTL . RSTO RD WE WO ROY . Provided by IHSNot for ResaleNo reproduction or networki
18、ng permitted without license from IHS-,-,-a DUTOUTPUTO W v R1 = 1.90 kn R2 = 4.5 ka CL = 50 pF on RDY, W, Ts6, CTTL CL 75 pF on FR, RD CL = 100 pF on FCLK CL = 170 pF on PHIl, PH12 CL = includes all stray capacitance. - cLT - I - - OUTPUT LOAD CIRCUIT FOR AC, FUNCTIONAL, AND THREE- STATE TESTS HIGI
19、2w* VIL PROGRAMMABLE LOAD CIRCUIT FOR AC, FUNCTIONAL, AND T H RE E - STAT E TESTS FIGURE 3. Switching test circuits and wavefoms. SIZE A. 5962-88599 STANDARDIZED MILiTARY DRAWING DEFENSE ELECTROC.IICC SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 10 IESC FORM 193A SEP 87 Provided by IHSNot f
20、or ResaleNo reproduction or networking permitted without license from IHS-,-,-XIN FCL K CTTL PHI I PHI2 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OH0 45444 DESC FORM 193A SEP 87 CLOCK SIGNALS i FIGURE 3. Switching test circuits and waveforms - Continued. Provided by IHS
21、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-I_-._- _I_- - I_-. - DESC-DWG-8577 57 m 7777775 0013055 7 M PHIl PH12 TC0 - WR - RD DeE -+Il- CONTROL OUTPUTS (PERIPHERAL CYCLE FIGURE 3. Switching test circuits and waveforms - Continued. SIZE A 5962-88599 STANDARD1
22、ZED MILITARY DRAWING MFENSE ELECTRONES SUPPLY CENTER REVISION LEVEL SHEET 12 DAYTON, OHIO 45444 )% FORM 193A SEP 87 . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-F DESC-DWG-8579 57 7777775 0033056 7 W - 7-7 /7 /“7 7- PH1 I PHI2 TSO - RD WR _I - D
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