DLA SMD-5962-87716 REV B-2011 MICROCIRCUIT LINEAR 8-CHANNEL JFET ANALOG MULTIPLEXER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. Editorial changes throughout. drw 00-12-13 Raymond Monnin B Redraw. Update drawing to current requirements. - drw 11-06-08 Charles F. SaffleTHE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACE
2、D. REV SHET REV SHET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND
3、 AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Wm. J. Johnson APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-CHANNEL, JFET ANALOG MULTIPLEXER, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-12-08 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-87716 SHEET 1 OF 12 DSCC FORM 2233 APR 97 596
4、2-E387-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87716 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device
5、 requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87716 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lea
6、d finish(see 1.2.3)1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 MUX-08A 8-channel JFET analog multiplexer 02 MUX-08B 8-channel JFET analog multiplexer 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-
7、1835 as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Positive supply voltage (
8、VCC) . +18 V dc Negative supply voltage (VEE) -18 V dc Logic input voltage . (-4 V or VEE) to VCCAnalog input voltage VEE- 20 V to VCC+ 20 V Maximum current through any pin . 25 mA Storage temperature range -65C to +150C Power dissipation (PD) 1/ . 500 mW Lead temperature (soldering, 60 seconds) 300
9、C Junction temperature (TJ) 150C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-case (JA): Case E . 91C/W Case 2 110C/W 1.4 Recommended operating conditions. Positive supply voltage (VCC) . +15 V dc Negative supply voltage (VEE) -15 V dc Ambient operatin
10、g temperature range (TA) -55C to +125C Digital “1” input voltage (VIH) 2.0 V min Digital “0” input voltage (VIL) 0.8 V max Analog voltage range (VA) . 10 V max _ 1/ Derate above 100C, 10 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
11、MICROCIRCUIT DRAWING SIZE A 5962-87716 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to t
12、he extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test
13、 Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist
14、.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence.
15、Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specifie
16、d herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved pro
17、gram plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not aff
18、ect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, a
19、ppendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram
20、shall be as specified on figure 3. 3.2.5 Switching time waveforms. The switching time waveforms shall be as specified on figure 7. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply ove
21、r the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted witho
22、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87716 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA+125C VCC= +15 V, VEE= -15 V Group A subgroups Device
23、type Limits Unit unless otherwise specified Min Max Positive supply current ICC1 All 12 mA 2, 3 15 Negative supply current IEE1 All -3.8 mA 2, 3 -5 “ON” resistance RON-10 V VSOURCE +10 V, 1 01 300 ISOURCE= 200 A 02 400 2, 3 01 400 02 500 “ON” resistance change with RON/ -10 V VSOURCE +10 V, 1 01 5 %
24、 change in source voltage VSOURCEISOURCE= 200 A 1/ 2 7 3 6 1 02 7 2 8 3 8 RONMATCH RONVSOURCE= 0 V, 1 01 15 % between switches MATCH ISOURCE= 200 A 1/, 2/ 2 20 3 18 1 02 20 2 23 3 23 Digital input current IINVIN= 0.4 V to 15 V 1 All 10 A 2, 3 20 Digital “0” enable current IIN(EN)VIN(EN)= 0.4 V 1 All
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