DLA SMD-5962-87518 REV D-2005 MICROCIRCUIT DIGITAL NMOS PROGRAMMABLE INTERRUPT CONTROLLER MONOLITHIC SILICON《硅单块 可编程序中断控制器N沟道金属氧化物半导体 数字微型电路》.pdf

《DLA SMD-5962-87518 REV D-2005 MICROCIRCUIT DIGITAL NMOS PROGRAMMABLE INTERRUPT CONTROLLER MONOLITHIC SILICON《硅单块 可编程序中断控制器N沟道金属氧化物半导体 数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87518 REV D-2005 MICROCIRCUIT DIGITAL NMOS PROGRAMMABLE INTERRUPT CONTROLLER MONOLITHIC SILICON《硅单块 可编程序中断控制器N沟道金属氧化物半导体 数字微型电路》.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add parameter ILIRto table I. Remove vendor CAGE 34335. Change drawing CAGE code. Editorial changes throughout. 89-03-01 Monica L. Poelking B Changes in accordance with NOR 5962-R022-99. LTG 99-01-28 Monica L. Poelking C Correct supply voltage ra

2、nge in paragraph 1.3. Delete IOHand IOLin footnote 4/ in table I. Update boilerplate. Editorial changes throughout. TVN 00-07-14 Monica L. Poelking D Update boilerplate to MIL-PRF-38535 requirements. CFS 05-08-22 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET RE

3、V D SHEET 15 REV D D D D D D D D D D D D D D REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 87-03-10

4、MICROCIRCUIT, DIGITAL, NMOS, PROGRAMMABLE INTERRRUPT CONTROLLER, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-87518 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL D SHEET 1 OF 15 DSCC FORM 2233 AP

5、R 97 5962-E409-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing

6、 describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87518 01 X X Drawing number Device type (see 1.2.1) Case outli

7、ne(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 8259A Programmable interrupt controller 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: O

8、utline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7 V dc Input volt

9、age range -0.5 V dc to +7 V dc Maximum power dissipation (PD) 1.0 W Storage temperature range -65C to +150C Lead temperature (soldering, 5 seconds). +270C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ). +150C 1.4 Recommended operating conditions. Supply voltag

10、e range (VCC) +4.5 V dc to +5.5 V dc Minimum low level input voltage (VIL). -0.5 V dc Minimum high level input voltage (VIH) . +2.3 V dc Maximum low level input voltage (VIL) +0.8 V dc Maximum high level input voltage (VIH) VCC+ 0.5 V dc Case operating temperature range (TC) . -55C to +125C Provided

11、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, stan

12、dards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integ

13、rated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL

14、-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence.

15、In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements.

16、The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has be

17、en granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications

18、to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This d

19、rawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions sh

20、all be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure

21、 2. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the f

22、ull case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

23、 from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein

24、. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall b

25、e marked on all non-JAN devices built in compliance to MIL-PRF-38535, Appendix A. The compliance indicator “C” shall be replaced with a “Q” or “QML” certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-P

26、RF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q” or “QML” certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in

27、MIL-HDBK-103 (see 6.7 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificat

28、e of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs age

29、nt, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

30、 IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A

31、 subgroups Min Max Unit Input low voltage VILVCC= 5 V 10% All 1, 2, 3 0.8 1/ V Input high voltage VIHVCC= 5 V 10% All 1, 2, 3 2.3 V Low level output voltage VOLVCC= 5 V 10%, IOL= 2.2 mA All 1, 2, 3 0.45 V High level output voltage VOHVCC= 5 V 10%, IOH= -400 A All 1, 2, 3 2.4 V IOH= -100 A 3.5 Interr

32、upt high level output voltage VOH (INT)VCC= 4.5 V IOH= -400 A All 1, 2, 3 2.4 V Input load current ILIVCC= 5.5 V VIN= 0.0 V to 5.5 V All 1, 2, 3 -10 2/ +10 A Input load current, IR0-IR7 ILIRVCC= 5.5 V VIN= 0.0 V to 5.5 V All 1, 2, 3 -300 2/ +10 A ILOLVCC= 5.5 V VOUT= 0.45 V to 4.5 V -10 2/ +10 Outpu

33、t leakage current ILOHVCC= 5.5 V, VOUT= VCC All 1, 2, 3 +10 A VCCsupply current ICCVCC= 5.5 V 3/ Outputs load static All 1, 2, 3 125 mA Input capacitance CINTC= +25C, fC= 1 MHz See 4.3.1d 4 10 I/O capacitance CI/O TC = +25C See 4.3.1d All 4 20 pF Functional test See 4.3.1c All 7, 8 A0/ CS setup to R

34、D /INTA falling tAHRLAll 9, 10, 11 0 ns A0/ CS hold after RD /INTA rising tRHAXAll 9, 10, 11 0 ns RD pulse width tRLRHAll 9, 10, 11 235 ns A0/ CS setup to WR falling tAHWLAll 9, 10, 11 0 ns A0/ CS hold after WR rising tWHAXAll 9, 10, 11 0 ns WR pulse width tWLWHSee figure 3 4/ All 9, 10, 11 290 ns S

35、ee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical

36、performance characteristics - Continued. Limits Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Min Max Unit Data setup to WR rising tDVWHAll 9, 10, 11 240 ns Data hold after WR rising tWHDXAll 9, 10, 11 0 ns Interrupt request width (low) 5/ tJLJHAll 9,

37、10, 11 100 ns Cascade setup to second or third INTA falling (slave only) tCVIALAll 9, 10, 11 55 ns End of RD to next command tRHRLAll 9, 10, 11 300 ns End of WR to next command tWHRLAll 9, 10, 11 370 ns Data valid from RD /INTA falling 6/ tRLDVAll 9, 10, 11 200 ns Data float after RD /INTA rising 6/

38、 tRHDZAll 9, 10, 11 10 2/ 100 ns Interrupt output delay 6/ tJHIHAll 9, 10, 11 350 ns Cascade valid from first INTA falling (master only) 6/ tIALCVAll 9, 10, 11 565 ns Enable active from RD falling or INTA falling 6/ tRLELAll 9, 10, 11 125 ns Enable inactive from RD rising or INTA rising 6/ tRHEHAll

39、9, 10, 11 150 ns Data valid from stable address 6/ tAHDVAll 9, 10, 11 200 ns Cascade valid to valid data 6/ tCVDVSee figure 3 4/ All 9, 10, 11 300 ns See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STAND

40、ARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. 1/ Due to the test equipment limitations, actual tested values may differ from those specified but specific li

41、mits are guaranteed. 2/ Guaranteed if not tested to the limits specified. 3/ ICCis measured in a static condition with outputs in a worst case state having standard IOL/IOHloads applied. 4/ Test conditions: VCC= 5 V 10%, VIL= 0.45 V, VIH= 2.4 V, VOL= 0.8 V, VOH= 2.0 V (see figure 3). 5/ This is low

42、time required to clear the input latch in the edge triggered mode. 6/ Test conditions: Capacitance of data bus: Maximum test = 100 pF, minimum test = 15 pF, CIN= 100 pF, CENABLE= 15 pF (see figure 3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

43、IZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type All Case outlines X and 3 Terminal number Terminal symbol Terminal number Terminal symbol 1 CS 15 CAS2 2 WR 16 SP / EN 3 RD 17 INT 4 D718

44、 IR0 5 D619 IR1 6 D520 IR2 7 D421 IR3 8 D322 IR4 9 D223 IR5 10 D124 IR6 11 D025 IR7 12 CAS0 26 INTA 13 CAS1 27 A014 GND 28 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAW

45、ING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 2. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER

46、 COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 NOTE: CLincludes jig capacitance. NOTES: 1. AC testing inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. 2. Timing measurements are made at 2.0 V for a logic “1” and 0.8 V for a logic “0”. FIGURE

47、 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 FIGURE

48、3. Test circuit and switching waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87518 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 12 DSCC FORM 2234 APR 97 NOTES: 1. Interrupt output must remain in HIGH at least until leading edge of first INTA . 2. Cycle 1 in iAPX86, and iAPX88 systems, the data bus is not active. FIGURE 3. Test circuit and switching waveforms - Continued. Provided by IHSNot for ResaleNo