DLA SMD-5962-85155 REV G-2006 MICROCIRCUIT MEMORY BIPOLAR PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单块 可编程逻辑阵列 双极主储存器 微型电路》.pdf

《DLA SMD-5962-85155 REV G-2006 MICROCIRCUIT MEMORY BIPOLAR PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单块 可编程逻辑阵列 双极主储存器 微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-85155 REV G-2006 MICROCIRCUIT MEMORY BIPOLAR PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单块 可编程逻辑阵列 双极主储存器 微型电路》.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE APPROVED E Removed vendor CAGE numbers 18324, 27014, and 34335. Added devices 21 and 22. Updated document format, editorial changes throughout. 96-06-13 M. A. Frye F Updated boilerplate. Removed vendor CAGE number 50364 from drawing. - glg 01-01-11 Raymond Monnin G Bo

2、ilerplate update, part of 5 year review. ksr 06-08-18 Raymond Monnin REV SHEET REV G G G SHEET 15 16 17 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James Jamison STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing DEFENSE SUPP

3、LY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-06-20 MICROCIRCUIT, MEMORY, BIPOLAR, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON A

4、MSC N/A REVISION LEVEL G SIZE A CAGE CODE 67268 5962-85155 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E582-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

5、43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as sho

6、wn in the following example: 5962-85155 01 R X | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit 01 PAL16L8-20 16-

7、input 8-output AND-OR invert gate array 02 PAL16R8-20 16-input 8-output registered AND-OR gate array 03 PAL16R6-20 16-input 6-output registered AND-OR gate array 04 PAL16R4-20 16-input 4-output registered AND-OR gate array 05 PAL16L8-30 16-input 8-output AND-OR invert gate array 06 PAL16R8-30 16-inp

8、ut 8-output registered AND-OR gate array 07 PAL16R6-30 16-input 6-output registered AND-OR gate array 08 PAL16R4-30 16-input 4-output registered AND-OR gate array 09 PAL16L8-15 16-input 8-output AND-OR invert gate array 10 PAL16R8-15 16-input 8-output registered AND-OR gate array 11 PAL16R6-15 16-in

9、put 6-output registered AND-OR gate array 12 PAL16R4-15 16-input 4-output registered AND-OR gate array 13 PAL16L8A-12 16-input 8-output AND-OR invert gate array 14 PAL16R8A-12 16-input 8-output registered AND-OR gate array 15 PAL16R6-12 16-input 6-output registered AND-OR gate array 16 PAL16R4-12 16

10、-input 4-output registered AND-OR gate array 17 PAL16L8-10 16-input 8-output AND-OR invert gate array 18 PAL16R8-10 16-input 8-output registered AND-OR gate array 19 PAL16R6-10 16-input 6-output registered AND-OR gate array 20 PAL16R4-10 16-input 4-output registered AND-OR gate array 21 PAL16R8-7 16

11、-input 8-output registered AND-OR gate array 22 PAL16R4-7 16-input 4-output registered AND-OR gate array 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP1-T20 20-lead d

12、ual-in-line package S CDFP5-F20 1/ 20-lead flat package 2 CQCC1-N20 20-terminal square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1/ Inactive for new design. Acceptable only for use in equipment designed or redesigned on or before 29 Novembe

13、r 1986. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. Supply volta

14、ge range 2/. -0.5 V dc to +7.0 V dc Input voltage range 2/ 3/. -0.5 V dc to +5.5 V dc Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) 4/ See MIL-STD-1835 Applied voltage to disabled output range 2/ 3/ -0.5 V dc to +5.5

15、V dc Maximum power dissipation (PD): 5/ Device types 01-04. 1.1 W Device types 05-08. 0.6 W Device types 09-22. 1.2 W Maximum junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC). 4.5 V dc minimum to 5.5 V dc maximum Minimum high level input voltage (VIH)

16、. 2.0 V dc Maximum low level input voltage (VIL) . 0.8 V dc Maximum high level output current (IOH) -2.0 mA dc Maximum low level output current (IOL) 12.0 mA dc Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The fol

17、lowing specification, standards and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing,

18、 General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcirc

19、uit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict bet

20、ween the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 2/ These ratings apply except for programming pins during a prog

21、ramming cycle. 3/ To ensure high speed operation, input logic levels must be maintained within these conditions. 4/ Heat sinking is recommended to reduce the junction temperature. 5/ Must withstand the added PDdue to short-circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or netw

22、orking permitted without license from IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL

23、-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be pr

24、ocessed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect

25、 the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appe

26、ndix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involvin

27、g no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.3.1c), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of fuses shall be programmed) or to any altered item drawing pattern which prog

28、rams at least 25 percent of the total number of fuses programmed. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified o

29、n figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall b

30、e the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For p

31、ackages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.6 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of co

32、nfigurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.6.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table II. It is recommended that users perform subgroups 7

33、and 9 after programming to verify the specific program configuration. 3.6.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing shall be satisfied by the manufacturer prior to d

34、elivery. 3.7 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the

35、QML flow option is used. 3.7.1 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved sourc

36、e of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7.2 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered

37、to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY

38、CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55oC TC +125oC unless otherwise specified Group A Subgroups Device type Min Max Unit Input clamp voltage VICVCC= 4.

39、5 V, II= -18 mA 1, 2, 3 All -1.5 V 01,02, 04-20 2.4 High Level output voltage VOHVCC= 4.5 V, VIL4.5 V, VIH2.0 V, IOH= -2 mA 1, 2, 3 03,21, 22 2.3 V Low level output voltage VOLVCC= 4.5 V, VIL4.5 V, VIH2.0 V, IOL= 12 mA 1, 2, 3 All 0.5 V High level input voltage VIH1, 2, 3 All 2 V Low level input vol

40、tage VIL1, 2, 3 All 0.8 V Pins CLK and OE 02,03,04,06,07,08, 10,11,12,14,15,16, 18,19,20 50 All others except I/O All 25 High level input current IIHVCC= 5.5 V, VI= 2.4 V All I/O ports 1, 2, 3 01,03, 04,05, 07,08, 09,11, 12,13, 15,16, 17,19, 20,21, 22 100 A Low level input current IILVCC= 5.5 V, VIL

41、= 0.4 V 1, 2, 3 All -0.25 mA Input current IIVCC= 5.5 V, VI= 5.5 V 1, 2, 3 All 1 mA 01-16 -30 -250 Output current short circuit 1/ IOSVCC= 5.5 V, VO= 0.5 V 1, 2, 3 17-22 -30 -130 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

42、om IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55oC TC +125oC unless otherwise

43、 specified Group A Subgroups Device type Min Max Unit Outputs -100 Off-state output current IOZLVCC= 5.5 V, VO= 0.4 V I/O ports 1, 2, 3 All -250 A Off-state output current IOZHVCC= 5.5 V, VO= 2.4 V 1, 2, 3 All 100 A 01-04 190 05-08 105 09-20 220 Supply current ICCVCC= 5.5 V, VI= 0 V Outputs open 1,

44、2, 3 21,22 210 mA Functional tests See notes for Table II All 7, 8 01,03,04 20 05,07,08 30 09,11,12 15 13,15,16 12 17,19,20 10 Propagation delay data input to output tPLH121,22 7 01,03,04 20 05,07,08 30 09,11,12 15 13,15,16 12 17,19,20 10 Propagation delay data input to output tPHL121,22 7 02 - 04 1

45、5 06 - 08 20 10 - 12, 14,16 12 18, 20 10 Propagation delay clock/up to output tPHL2See figure 3 9, 10, 11 21, 22 7 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-85155 STANDARD MICROCIRCUIT DRAWING DEFEN

46、SE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55oC TC +125oC unless otherwise specified Group A Subgroups Device type Min Max Unit 02 - 04 15

47、 06 - 08 20 10 - 12, 14,16 12 18 - 20 10 Propagation delay clock/up to output tPLH221, 22 7 01,03,04 25 05,07,08 30 09,11,12 17 13,15,16 14 17,19,20 12 Propagation delay output high impedance to output high tPZH121,22 9 01,03,04 25 05,07,08 30 09,11,12 17 13,15,16 14 17,19,20 12 Propagation delay ou

48、tput high impedance to output low tPZL121,22 9 01,03,04 20 05,07,08 30 09,11,12 15 13,15,16 12 Propagation delay output high to output high impedance 2/ tPHZ1See figure 3 9, 10, 11 17,19, 20,21, 22 10 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-85155 STA