DLA SMD-5962-82021 REV F-1992 MICROCIRUITS MICROPROCESSOR 16-BIT N-CHANNEL MONOLITHIC SILICON《硅单片16比特N沟道微处理器微型电路》.pdf

《DLA SMD-5962-82021 REV F-1992 MICROCIRUITS MICROPROCESSOR 16-BIT N-CHANNEL MONOLITHIC SILICON《硅单片16比特N沟道微处理器微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-82021 REV F-1992 MICROCIRUITS MICROPROCESSOR 16-BIT N-CHANNEL MONOLITHIC SILICON《硅单片16比特N沟道微处理器微型电路》.pdf（31页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-5962-8202L REV F W 9999996 0026085 72T REVISIONS DESCRIPTION DATE (YR-MO-DA) APPROVED LTR A Table I: Add VOL parameters. 1.3: Change PD from 1.5 W to 84-03-02 M. A. Frye 1.75 U. B Revise table 1 limits, add 10 MHz device, revise operating 85-12-16 M. A. Frye C Convert to military drawing format,

2、 inactivate parts which have a 87-04-23 M. A. Frye temperature range, and revise waveforms. QPL source, change parameters 28, 57, and 58 in table I and the corresponding waveforms on figure 6. to drawing. Add vendor CAGE number 50088 Editorial changes throughout document. D Add device type 04. Chang

3、es to 1.3 and 1.4. Changes to tables I 88-04-01 M. A. Frye Change CAGE number to 67268. and II. Delete vendor CAGE number 04713 as approved source for O1 device. Editorial changes throughout document. Delete figures 2 and 3. E I Add case outline U. Change case T dimensions on figure 1. Add I vendor

4、CAGE 18324 as supplier for device 01. Editorial changes 89-1 1-16 M. A. Frye I I throughout. I l F 1.3: Modify thermal resistance for case U from 2OoC/W to 10C/W; 92-10-05 additions and corrections to figure 1, case outline U; delete vendor CAGE number 18324 as an approved source; change vendor CAGE

5、 number 50088 to 18778. THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED CURRENT CAGE CODE 67268 SHEET SHEET 15 16 17 REV STATUS OF SHEETS PMIC NIA STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A w SHEET P

6、REPARED BY Christopher A. Rauch CHECKED BY Ray Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 1983-09-28 REVISION LEVEL F DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUITS, MICROPROCESSOR, 16- BIT, N-CHANNEL, MONOLITHIC SILICON I I 82021 SHEET 1 OF 29 )ESC FORM 193 JUL 91

7、DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-ES00 Licensed by Information Handling ServicesProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-8202L REV F 9999996 0026086 bbb 1. SCOPE 1.1 Seopc. This dra

8、wing describes device rquirments for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. 1.2 Part or Identifvinp Number (PIN). The complete PIN shall be as shown in the following example: i I Lead finis

9、h per I I I NIL-M-38510 i- Case outline (1.2.21 T I T Drawing number Devi ce type (1.2.1) 1.2.1 Device tvDe(s). The device typds) shall identify the circuit function as follows: Device typc Generic number circuit function o1 68ooO-6 16-bit fixed instruction microprocessor o2 68ooo-a l-bit fixed inst

10、ruction microprocessor 03 68ooO-10 l-bit fixed instruction microprocessor o4 68000-12 l-bit fixed instruction microprocesaor 1.2.2 Case outline(s). The case outline($) shall be as designated in MIL-STD-1835, and as follows: Out Line letter Descriptive designator Terminals Peckme style T CMGA2-PN 68

11、Grid array U See figure 1 68 Leaded chip carrier X CQCCl-W68 68 Square leadless chip carrier with thermal pad Y CDIPl-T IIIH1 I VIN = 5.25 V I - I I I I I I I I I I l Lowet output voltage IVoL4 I I IoL = 5.0 IIIA I - I 7,2,3 I I 0.5 I V RESET I I I 1 I I I state) output current I (HIGH) I I I I I I

12、I I I.rA state) output current I I I I I I I I all inputs z/ Hi-evwt current IIIH2 i HALT, RESET I I I I I I I I I I I l I 1,2,3 I -2.5 1 Icu LOU level input current; liILl I VIN = O v I - all inputs 2/ I I I I I I I Lwuvemt current I IIU i HALT, RESET I I I I I I I I I I I 1,2,3 I -20 I IW I - I I

13、I I I I I t I l I l l I I I I I l I I Supply current IIcc I vcc = 5.25 v y I - I 1,2,3 I I 333 I nA I I I Capacitance i 20 i pF I I = O V, frequency = I MHZ i - i4 i !IN YiN ee 4.3.1) I l I I I I I 1 I l I I I I I 7,8 I I I I See 4.3.ld I - Functional tests I See footnotes at end of table. DESC FORM

14、 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-82021 REV F I 9999996 0026089 375 I 1 Clock rise time IfCr I TABLE I. Electrical performance characteristics - Continued. I i I I I 1 I i l i I I I l impedance (maximum) STANDARDIZ

15、ED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Clock high to ItCHAD i address data high SIZE 8202 1 r REVISION LEVEL SHEET F 5 Cl-k high to As, itcHsL i DS low (maximum) Cl-k high to As, itCHSLn i DC high (minimum) I - I I Address to AS,JS ItAvsL I (read) low/ AS write i i

16、- FC valid to AS,DS itFcvsL i (read) Low/ AS write - Clock low to AS, DS ItCLSH I high - I I AS, DS high to I SHAF I I addresslFC invalid 1 (read)/AS write E, 0s wioh low ItsL 1 DS width low (write) ItDSL - I I jwaveform j i Device i Device i Device 1 Device illnit I number 1Group I type 01 I type 0

17、2 I type 03 I type 04 I 6 MHz I 8 MHz 10 MHr 12.5 MHzl 1 J Min Hax Min Max Min Max Min bx I I I I I I i 1 9,lO,lli 167 I 2 I9,10,111 75 i 3 9,10,11i 75 I 4 9,10,11 5 9,10,11 I I 1 I 6 19,10,111 E I 7 s/ 19,10,111 I 1 250i 1251 2501 100 _/_ti_ 1251 551 1251 45 2501 801 2501 ns 1251 351 1251 ni 1251 3

18、51 1251 ns 101 I 51 ns 101 5 ns 601 I 551 ns _t_t_t_ - - I I I O I 01 i O1 1 01 I ns I I I I I 1 I I I 14 19,10,111 3371 1 2401 1 1951 1 160 14A 9,10,11 170 1151 95 1 80 I ns I I l I I i 1 s/ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without

19、license from IHS-,-,-TABLE I. Electrical Derformance characteristics - Continued. I 1 I I I I I 4.75 V 5 V S 5.25 V (see A sub- 6 MHr 1 8 MHz IO WHz I 12.5 WHz Test I -1 I Conditions I/ JWaveform 1 1 Device 1 Device I Device I Device IUnit I -55C = TC = +llOC I number lroup I type 01 I type O2 I typ

20、e 03 I type O4 I Nin Max Win tax Min Hax Min Nax I I unless %herwise figure 3) I I spec if ied I I I I I I 15 9,10,11 18Oi i 150/ I 105i i 65/ I ns - 9/ g/ I I I I I I I - AS, DS width high itgH i GND * O V Clsk high to E, I DS high impedance ItWCZ I c- AS, DS high to R/ itSHRH i high I Clock high t

21、o R/ high (maximum) tCHRH i I Clock high to R/ high (niniaun) itcHRHn 1 Clock high to R/ ItCHRL I Low i E low to R/ valid itASRV I I I e- Al-A23 SIZE A STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 82021 REVISION LEVEL SHEET FIGURE 3. Switching test circuit and w

22、aveforms - Continued. I I F I 21 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-82023 REV F 7999996 O026306 284 FCO-FC2 CLK m mm As casmas )c Bus arbitration timing diagram - multiple bua riqwsts STANDADIZED MILITARY D

23、RAWING DEFENSE ELECTRilICS SUPPLY CENTER DAYTON, OIO 45444 SIZE a2021 A REVISION LEVEL SHEET P 22 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-PROCESSOR STATUS STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CEWTER DAYTON, OHIO 45444 PERI

24、PHERAL CONTROL SIZE A GND (2) CLK - _c - FCO FC 1 - FC2 - VMA - VPA _c c ESET - SYSTEM CONTROL MICROPROCESSOR FIGURE 4. Input and output sianals. Ai-A23 ADDRESS BUS 00-Di5 - UDS _cc - LOS OTACK - ASYNCHRONOUS CONTROL + BUS E - SE BUS ARBITRATION BGACK I J c- I - IPLO - INTERRUPT CONTROL c- IPL I 820

25、2 1 REVISION LEVEL I SEIEET I I F I 23 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-59b2-2021 REV F W 9999996 002bL08 O57 STAtJDARDIZED MILITARY DRAWIUG DEFBHSE ELECTRONICS SUPPLY CEMTER DAYTOU, OHIO 45444 3.8 Notificatio

26、n of change. Notification of change to DESC-ECC shall be required in accordance with HIL-STD-883 (see 3.1 herein). SIZE 8202 1 A REVISION LEVEL SHEET F 24 3.9 Verification and review, DESC, DESCs agent, and the acquiring activity retain the option to review the Offshore documentation shalC be de ava

27、ilable onshore mufacturerls facility and applicable required documtation. mt the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspcction. Sanpling and inspection procedures shall be in accordance with section 4 of HIL-H-38510 to the extent specified in MIL-STD-883 (see 3.

28、1 herein). 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additions1 criteria shall apply: a. Burn-in teat, method 1015 of MIL-STD-883. (1) Test condition A, B, C, D, or E u

29、sing the circuit submitted with the certificate of compliance (see 3.6 herein). (2) TA = +12SoC, mininui. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufactur

30、er. b. 4.3 uality conformance inspection. Quality conformance inspcction shall be in accordance with method 5005 of ML-STD-883 inchding groups A, B, C, and 0 inspections. The following additional criteria shall apply. 4.3.1 Group A inspcction. a. Tests shall be as specified in table II herein. b. Su

31、bgroups 5 and 6 in table i, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CI, measurement) shall be measured only for the initial test and after process or design changes which may affect input capacitance. A minisur sample size of 5 devices with zero rejects shall be required. Subgrou

32、ps 7 and 8 shall consist of verifying the functionality of the device. The instruction set forms a part of the vandors test tape and shall be maintained and available fn the approved sources of supply. 4.3.2 GKWIDS C and D inspections. a. End-point electrical parameters shall be as specified in tabl

33、e IX herein. b. Steady-state life test condltions, method 1005 of HIL-STD-883. (1) Test condition A, B, C, D, or E using the circuit submitted vith the certificate of colpliance (see 3.6 herein). d. (2) TA = +12SoC, mininum. (3) Test duration: 1,ooO hours, except as pernitte by method 1005 of MIL-ST

34、D-883. DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-82021 REV F 999999b 0026109 T93 STANDARDIZED HILI TARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 TABLE II. Electrical test reauirements. SIZE 820

35、21 A REVISION LEVEL SEET F 25 i i I Subgroups I I (per method I I 5005, table I) I I I I I interim electrical parameters I 1, 7 I I (method 5004) I I t I I I 9, 10, 11 I I Group A test requirements I 1, 2, 3, 4, 7, I I (nethod 5005) I 8, 9, 10, 11 I I I I Groups C and 0 end-point I I electrical para

36、meters I only) I I (method 5005) I I i 1 MIL-STD-883 test rquirements I I Final electrical test parameters I I*, 2*, 7, I 1 (nethod 5004) I8 (at llOC only)( I I 2, 8 (at llOC I it. PDA applies to subgroup 1 or 2. 5. PACKAGING 5.1 6. NOTES Packwing reauirements. The requirements for packaging shall b

37、e in accordance with MIL-fi-38510. 6.1 Intended use. Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the rquired function are not available for OEM application. listing on QPL-38510, the device s

38、pecified herein will be inactivated and will not be used for neu design. QPL-38510 product shall be the preferred item for all applications. 6.2 Replaceability. Replaceability is determined as follows: When a military specification exists and the product covered by this drawing has been qualified fo

39、r The a. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. Uhen a QPL source is established, the device specified in this drawing will be replaced by the microcircuit identified as part number M38510/540-8-. b. 6.3 C

40、onfiguration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of This coordination will be acconplished in accordance with MIL-STD-481 using DD record for the individual documents. Form 1693, Engineering Change Proposal (Short Form). 6.4 Record of users. Mili

41、tary and industrial users shall inform Defense Electronics Supply Center when a system application requires configuration control and the applicable SMD. will be used for coordination and distribution of changes to the drawings. microelectronics devices (FSC 5962) should contact DESC-ECT, telephone

42、(513) 296-6022. DESC will maintain a record of users and this list Users of drawings covering 6.5 Comments. Comments on this drawing should bc directed to DESC-ECC, Dayton, Ohio 45444, or telephone (513) 296-8526. DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permi

43、tted without license from IHS-,-,-SMD-5962-8202L REV F W 999999b 002bLLO 705 W I I I I l I I I I I I Address bus (Al throwh A23). This 23-bit, unidirectional, three-statc bus is capable of addressing 8 megawords of data. During interrupt cycles, address lines AI, A2, and A3 provide inforlistion abou

44、t what level interrupt is being serviced while address lines A4 through A23 are all set to a logic high. transfer and accept data in either word or byte length. supplies the vector nuher on data lines 00 through 07. It provides the address for bus operation during all cycles except interrupt cycles.

45、 Data bus (D thrwah DIS). This 16-bit, bidirectional, three-state bus is the general purpose data path. It can During an interrupt acknowledge cycle, the external device I I I I I I STANDARD1 ZED MILITARY DRAWING DEFEWSE ELECTRONICS SUPPLY CENTER DAYTOIO, OHIO 45444 SIZE 8202 1 A REVISION LEVEL SHEE

46、T F 26 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-82021 REV F m 999999b 002b111 641 m STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Asynchronous bus control. Asynchronous data transfers are handled u

47、sing the following control signals: Address strobe, read/write, upper and louer data strobes, and data transfer acknowledge. f o1 lowing paragraphs. These signals are explained in the Address strobe (As). Read/write (R/). This signal indicates that there is a valid address on the address bus. This s

48、ignal defines the data bus transfer as a read or write cycle. The R/ signal also works in conjunction with the upper and lower data strobes as explained in the following paragraph. - Upper and lower data strobes (UDS, LDS). These signals control the data on the data bus as shown in table IV. When Uh

49、m the R/U line is low, the processor the R/ line is high, the processor will read from the data bus as indicated. will write to the data bus as shown. TABLE IV. Data strobe control of data bus. SIZE 8202 1 A REVISION LEVEL SHEET F 27 iR/ i D8-DI 5 DO-D7 i t t I l l I I I I I 1 High I High I I No valid data I