DLA SMD-5962-82005 REV F-2010 MICROCIRCUITS MEMORY DIGITAL 65 536 (8K X 8) UV ERASABLE PROM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED D Change to Military drawing format. Add new vendor CAGE 61394. Add 2 new device types. Editorial changes throughout. Change drawing CAGE to 67268. 87-08-31 N. A. HAUCK E Updated boiler plate paragraphs. Added D certification paragraphs. ksr 05-02-

2、10 Raymond Monnin F Boilerplate update, part of 5 year review. ksr 10-11-15 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHEET REV F F F F F F F F SHEET 15 16 17 18 19 20 21 22 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2

3、3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY SANDRA ROONEY DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DICENZO THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY N. A. HAUCK MICROCIRCUITS,MEMORY, DIGITAL, 65

4、,536 (8K X 8), UV ERASABLE PROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 26 May 1982 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 14933 82005 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E068-11 Provided by IHSNot for ResaleNo reproduction or networking permitted

5、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in acc

6、ordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 82005 01 Y A | | | | | | | | | | | _ | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device t

7、ype(s) shall identify the circuit function as follows: Device type Generic number Circuit Access Program method 01 2764-450 8192 x 8 - Bit UV EPROM 450 ns A,C 02 2764-250 8192 x 8 - Bit UV EPROM 250 ns A,C 03 2764A-35 8192 x 8 - Bit UV EPROM 350 ns B 04 2764A-25 8192 x 8 - Bit UV EPROM 250 ns B 05 2

8、764A-20 8192 x 8 - Bit UV EPROM 200 ns B 06 2764-150 8192 x 8 - Bit UV EPROM 150 ns C 07 2764-200 8192 x 8 - Bit UV EPROM 200 ns C 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style Y GDIP1-

9、T28 or CDIP2-T28 28 dual-in-line package 1/ Z CQCC1-N32 32 rectangular leadless chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage, VCC-0.3 to 7.0 V 2/ Storage temperature range -65C to +150C Maximum power dis

10、sipation, PD 1.0 W Lead temperature (soldering, 10 seconds) .300C. Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) Device types 03 - 05 .+150C Device types 01, 02, 06, 07 +175C All input or output voltages with respect to ground for device types 03 - 05 .-0.6 V t

11、o 6.25 V Input voltage range for device types 01, 02, 06, 07 -0.3 V dc to 7.0 V dc VPPSupply Voltage (methods A and C) -0.3 V to 22 V (method B)-0.6 V to 13 V 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to VSS. Provided by IHSNot for ResaleNo reproduct

12、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Case operating temperature range -55C to +125C Input low voltage, V

13、IL-0.1 V to 0.8 V Input high voltage, VIH2.0 to VCC+1 Supply voltage, VCC4.5 V to 5.5 V High level program input voltage VIN(PR). 21.0 V .5 V (Program methods A and C) High level program input voltage VIN(PR). 12.5 V 0.3 V (Program method B) 2. APPLICABLE DOCUMENTS 2.1 Government specification, stan

14、dards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integ

15、rated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL

16、-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict b

17、etween the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requ

18、irements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional

19、certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements here

20、in. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified

21、 to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal conne

22、ctions. The terminal connections shall be as specified on figure 1. 3.2.2 Truth tables. The truth tables shall be as specified on figure 2. 3.2.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2 herein.

23、 When required, in screening (see 4.2 herein), or quality conformance inspection groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or similar pattern (a minimum of 50 percent of the total number of bits programmed). 3.2.2.2 Pro

24、grammed devices. The requirements for supplying programmed devices are not part of this document. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVE

25、L F SHEET 4 DSCC FORM 2234 APR 97 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance chara

26、cteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Markin

27、g shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MI

28、L-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535 the “D” certification mark shall be used in plac

29、e of the “C“ certification mark. 3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics sp

30、ecified in 4.4. 3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.6.3 Verification of erasure or programmability of EPROMS. When specified, devices shall be verified as either programmed

31、to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and shall be removed from the lot. 3.7 Certi

32、ficate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall a

33、ffirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9

34、Notification of change. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.10 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agen

35、t, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.11 Microcircuit group assignment for device class M. Device class M devices covered by t

36、his drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5

37、DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC 125C Group A subgroups Device type Limits Unit Min MaxHigh level output voltage VOHIOH= -400 A VIL= 0.8 V, VIH= 2.0 V VCC= 4.5 V 1, 2, 3 01,02,06, 07 2.4 V VCC= 5.25 V 03 - 05 2.4 Low level output v

38、oltage VOLIOL= 2.1 mA VIL= 0.8 V, VIH= 2.0 V VCC= 5.5 V 1, 2, 3 01,02,06,07 0.4 V VCC= 5.25 V 03 - 05 0.45 Low level output leakage current IOLVCC = 5.5 1/ VOUT= 0.1 V1, 2, 3 ALL 10 A High level output leakage current 2/ IOHVCC = 5.5 V 1/ VOUT= 5.5 V 1, 2, 3 ALL 10 A High level input current 2/ IIHV

39、CC= 5.25 V Outputs deselected VIN= 5.25 V1, 2, 3 ALL 10 A Low level input current 2/ IILVCC= 5.25 V Outputs deselected VIN= 0.4 V1, 2, 3 ALL -10 A VPPsupply current read IPPVPP= 5.5 V1, 2, 3 ALL 5 mA Supply current (standby) ISBOutput open CE = VIHVCC= 5.5 V 1, 2, 3 01, 02, 06, 07 60 mA VCC= 5.25 V

40、03 - 05 40 Supply current ICCOutput open OE = CE = VILVCC= 5.5 V 1, 2, 3 01, 02, 06, 07 120 mA VCC= 5.25 V 03 - 05 100 High level input leakage current IIHVCC= 5.5 V VIN= 5.5 V 1, 2, 3 01, 02, 06, 07 1 A 03 - 05 10 Low level input leakage current IILVCC= 5.5 V VIN= 0.1 V 1, 2, 3 01, 02, 06, 07 1 A 0

41、3 - 05 -10 High level input voltage VIHVCC= 4.5 V 3/1, 2, 3 ALL 2.0 6.5 V Low level input voltage VILVCC= 5.5 V 3/1, 2, 3 ALL -0.1 0.8 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

42、 A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC 125C Group A subgroups Device type Limits Unit Min Max VPPread voltage VPP1, 2, 3 ALL VCC-0.7 VCC+1 V In

43、put capacitance 2/ 4/ CINVIN= 0V TC= +25C f = 1 MHz See 4.3.1c 4 All 6 pF Output capacitance 4/ COUTVOUT= 0V TC= +25C f = 1 MHz See 4.3.1c 4 All 12 pF Address access time tAAVCC= 5.25 V 2/ 5/ See figure 5 9, 10, 11 06 150 ns 05, 07 200 01 450 02, 04 250 03 350 Chip enable access time tCE9, 10, 11 06

44、 150 ns 05, 07 200 01 450 02, 04 250 03 350 Output enable access time tOE9, 10, 11 03 15 130 ns 01 15 200 02, 04, 06 10 100 05, 07 0 150 Chip enable or Output enable to high Z tDF6/ 9, 10, 11 03 0 115 ns 01 5 150 02 0 90 04 0 60 05, 07 0 150 06 0 80 Output hold from address change tOH6/ 9, 10, 11 Al

45、l 0 ns 1/ Connect all address inputs and OE to VIHand measure IOLand IOHwith the output under test connected to VOUT. 2/ Outputs shall be loaded per figure 4. 3/ Tests for all inputs and control pins. 4/ All pins not being tested are to be grounded. 5/ Equivalent ac test conditions (actual load cond

46、itions vary by tester): Output load: 1 TTL gate and CL= 100 pF. Input rise and fall times 20 ns. Input pulse levels: 0.4 V and 2.4 V. 6/ Tested initially and after any design changes. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

47、UIT DRAWING SIZE A 82005 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 Device Types All Case Outlines Y Z Terminal Number Terminal Symbol Terminal Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VPPA12 A7

48、A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSSQ3 Q4 Q5 Q6 Q7 CE A10 OE A11 A9 A8 NC PGM VCC NC VPPA12 A7 A6 A5 A4 A3 A2 A1 A0 NC Q0 Q1 Q2 VSSNC Q3 Q4 Q5 Q6 Q7 CE A10 OE NC A11 A9 A8 NC PGM VCC FIGURE 1. Terminal connections. Pin names A0 A12Addresses CE Chip enable OE , Output enable Q0 Q7Outputs PGM Program pin Option A with active terminals on plane 1. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAND