DLA SMD-5962-06208-2006 MICROCIRCUIT DIGITAL CMOS DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《硅单片数字信号处理机氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-06208-2006 MICROCIRCUIT DIGITAL CMOS DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《硅单片数字信号处理机氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-06208-2006 MICROCIRCUIT DIGITAL CMOS DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《硅单片数字信号处理机氧化物半导体数字微型电路》.pdf（83页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET 75 76 77 78 79 80 81 82 REV SHEET 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 REV SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV

2、STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles F. Saffle COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED

3、BY Thomas M. Hess MICROCIRCUIT, DIGITAL, CMOS, DIGITAL AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 06-09-25 SIGNAL PROCESSOR, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-06208 SHEET 1 OF 82 DSCC FORM 2233 APR 97 5962-E265-06 Provided by IHSNot for Resal

4、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels co

5、nsisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the

6、 PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 06208 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device clas

7、ses Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA

8、device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 SMJ320F2812 Digital signal processor 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as foll

9、ows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outl

10、ine(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CQCC2-F172 172 Quad leaded chip carrier with non-conductive tie bar 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535

11、, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximu

12、m ratings. 1/ Supply voltage ranges, (VDDIO, VDDA1, VDDA2, VDDAIO, AVDDREFBG) -0.3 V to +4.6 V Supply voltage ranges, (VDD, VDD1) . -0.5 V to +2.5 V VDD3VFLrange -0.3 V to +4.6 V Input voltage range, (VIN) -0.3 V to +4.6 V Output voltage range, (VO) . -0.3 V to +4.6 V Input clamp current, IIK(VINVDD

13、IO) . 20 mA 2/ Output clamp current, IOK(VOVDDIO) 20 mA Operating ambient temperature range, (TA) -55C to +125C 3/ Storage temperature range, (TSTG) -65C to +150C 3/ On-Chip Analog-to-Digital Converter. Supply voltage ranges, (VSSA1/VSSA2to VDDA1/VDDA2/AVDDREFBG) . -0.3 V to +4.6 V Supply voltage ra

14、nges, (VSS1to VDD1) . -0.3 V to 2.5 V Analog input (ADCIN) clamp current, total (max) 20 mA 4/ 1.4 Recommended operating conditions. Device supply voltage, I/O, (VDDIO) . +3.14 V to +3.47 V Device supply voltage, CPU, (VDD, VDD1): 1.8 V (135 MHz) +1.71 V to 1.89 V 1.9 V (150 MHz) +1.81 to +2 V Suppl

15、y ground, (VSS) . 0 V ADC supply voltage (VDDA!, VDDA2, AVDDREFBG, VDDAIO) +3.14 V to +3.47 V Flash programming supply voltage, (VDD3VFL) . +3.14 V to +3.47 V Device clock frequency (system clock), (fSYSCLKOUT): VDD= 1.9 V 5% 2 MHz to 150 MHz VDD= 1.8 V 5% 2 MHz to 135 MHz High level input voltage,

16、(VIH): All inputs except XCLKIN +2 V to VDDIOXCLKIN ( 50 A max) +0.7VDDto VDDMaximum low level input voltage, (VIL): All inputs except XCLKIN +0.8 V XCLKIN ( 50 A max) +0.3VDDMaximum high level output source current, VOH= 2.4 V (IOH): All I/Os except group 2 -4 mA Group 2 5/ -8 mA Maximum low level

17、output sink current, VOL= VOLmax (IOL): All I/Os except group 2 4 mA Group 2 5/ 8 mA Operating ambient temperature range, (TA) . -55C to +125C Flash Timing. Minimum flash endurance for the array (Nf) (Write/erase cycles) (0C to 85C) . 100 cycles 6/ Maximum One-Time Programmable (OTP) endurance for t

18、he array (NOTP) (Write cycles) (0C to 85C) . 1 write _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recomm

19、ended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Continuous clamp current per pin is 2 mA. 3/ Long term high temperature storage and/or extended use at maximum temperature conditions may result in a reduc

20、tion of overall device life. 4/ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDAor below VSS. The continuous clamp current per pin is 2 mA. 5/ Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1. 6/ Flash Timing End

21、urance is the minimum number of write/erase or write cycles specified over a programming temperature range of 0C to 85C. Flash may be read over the operating temperature range of the device (-55C to +125C). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

22、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

23、 of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDAR

24、DS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available on

25、line at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited he

26、rein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

27、 MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-385

28、35, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for devi

29、ce class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 2. 3.2.4 Timing waveforms an

30、d test circuits. The Timing waveforms and test circuits shall be as specified on figures 3 39. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as sp

31、ecified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked

32、with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the

33、 RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

34、NDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The complian

35、ce mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein).

36、 For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall

37、affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V i

38、n MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired t

39、o this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation

40、shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking pe

41、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified

42、Group A subgroups Device type Limits Unit Min MaxElectrical Characteristics Over Recommended Operating Conditions IOH= IOHmaximum 2.4 High-level output voltage VOHIOH= 50 A VDDIO 0.2 V Low-level output voltage VOLIOL= IOLmaximum 0.4 V With pullup. VDDIO= 3.3 V, VIN= 0 V, All I/Os (including XRS) exc

43、ept EVB 1/ -80 -190 With pullup. VDDIO= 3.3 V, VIN= 0 V, GPIOB/EVB -13 -35 Low-level input current IILWith pulldown. VDDIO= 3.3 V, VIN= 0 V 2 A With pullup. VDDIO= 3.3 V, VIN= VDD2 High-level input current IIHWith pulldown. 2/ VDDIO= 3.3 V, VIN= VDD28 80 A High-impedance (offstate) state output curr

44、ent IOZVO= VDDIOor 0 V 1, 2, 3 2 A Input capacitance Ci7 TYP pF Output capacitance Co4 7 TYP pF Operational mode 3/ 230 8/ mA IDLE mode 4 150 8/ mA STANDBY mode 5/ 6/ 10 8/ mA IDDHALT mode 6/ 7/ 70 TYP A Operational mode 3/ 30 8/ mA IDLE mode 4 10 8/ mA STANDBY mode 5/ 6/ 20 8/ A Quiescent supply cu

45、rrent IDDIOHALT mode 6/ 7/ 1, 2, 3 All 20 8/ A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06208 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEE

46、T 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxOperational mode 3/ 45 8/ mA IDLE mode 4 4 8/ A STANDBY mode 5/ 6/ 4 8/ A IDD3VFLHALT mode 6/ 78/ A

47、Operational mode 3/ 50 8/ mA IDLE mode 4 20 8/ A STANDBY mode 5/ 6/ 20 8/ A Quiescent supply current IDDA9/ HALT mode 6/ 7/ 1, 2, 3 All 20 8/ A Device Clocks 10/ Cycle time 28.6 50 ns On-chip oscillator clock tc(OSC)Frequency 20 35 MHz Cycle time 6.67 250 ns XCLKIN tc(CI)Frequency 4 150 MHz Cycle ti

48、me 6.67 500 ns SYSCLKOUT tc(SCO)Frequency 2 150 MHz Cycle time 6.67 2000 ns XCLKOUT tc(XCO)Frequency 0.5 150 MHz Cycle time 6.67 ns HSPCLK tc(HCO)Frequency 150 MHz Cycle time 13.3 ns LSPCLK tc(LCO)Frequency 75 MHz Cycle time 40 ns ADC clock tc(ADCCLK)11/ Frequency 25 MHz Cycle time 50 ns SPI clock tc(SPC)Frequency 20 MHz Cycle time 50 ns McBSP tc(CKG)Frequency 20 MHz Cycle time 6.67 ns XTIMCLK tc(XTIM)Frequency 9, 10, 11 All 150 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking perm