DLA DSCC-VID-V62 13602-2013 MICROCIRCUIT DIGITAL LINEAR 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 13602-2013 MICROCIRCUIT DIGITAL LINEAR 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 13602-2013 MICROCIRCUIT DIGITAL LINEAR 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(12页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original
2、date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL LINEAR, 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS, MONOLITHIC SILICON 13-02-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13602 REV PAGE 1 OF 12 A
3、MSC N/A 5962-V046-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performan
4、ce microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering document
5、ation: V62/13602 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74AVCB164245-EP 16 bit dual supply bus transceiver with configurable voltage translation and 3-state outputs 1.2.2 Case ou
6、tline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-153 Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator
7、 Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 3 1.3 Absolut
8、e maximum ratings. 1/ Supply voltage range: VCCA-0.5 V to 4.6 V VCCB-0.5 V to 4.6 V Input voltage range, (VI) 2/ I/O ports (A port) . -0.5 V to 4.6 V I/O ports (B port) . -0.5 V to 4.6 V Control inputs -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, (VO)
9、 2/ A port -0.5 V to 4.6 V A port -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, (VO) 2/ 3/ A port -0.5 V to VCCA+ 0.5 V A port -0.5 V to VCCB+ 0.5 V Input clamp current, (IIK) (VI 0) -50 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) .
10、50 mA Continuous current through VCCA, VCCB, or GND 100 mA Maximum junction temperature, (TJ) 150 C Storage temperature range -65C to 150C 1.4 Thermal characteristics. Thermal metric 4/ Case outline X Units Junction to ambient thermal resistance, JA5/ 59.9 C/W Junction to case (top) thermal resistan
11、ce, JCtop6/ 13.9 Junction to board thermal resistance, JB7/ 27.1 Junction to top characterization parameter, JT8/ 0.5 Junction to board characterization parameter, JB9/ 26.8 Junction to case (bottom) thermal resistance, JCbot10/ N/A 1/ Stresses beyond those listed under “absolute maximum ratings” ma
12、y cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
13、 device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The output positive voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 4/ For more information about traditional an
14、d new thermal metrics, see manufacturer data. 5/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The junction to case (top) thermal resistance is
15、obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to cont
16、rol the PCB temperature, as described in JESD51-8. 8/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The ju
17、nction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The junction to case (bottom) thermal resistance is obtained by
18、 simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS,
19、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 4 1.4 Recommended operating conditions. 11/ 12/ 13/ 14/ VCCIVCCOLimits Unit Min Max Supply voltage VCCA1.4 3.6 V VCCB1.4 3.6 High level input voltage, (VIH) Data inputs 1.4 V to 1.95 V VCCIx 0.65 1.95 V to 2.7 V 1.7 2.7 V to 3.6 V 2 Low lev
20、el input voltage, (VIL) Data inputs 1.4 V to 1.95 V VCCIx 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 High level input voltage, (VIH) Control inputs (referenced to VCCB) 1.4 V to 1.95 V VCCBx 0.65 1.95 V to 2.7 V 1.7 2.7 V to 3.6 V 2 Low level input voltage, (VIL) Control inputs (referenced to VCCB)
21、 1.4 V to 1.95 V VCCBx 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 Input voltage, (VI) 0 3.6Output voltage, (VO) Active state 0 VCCO3-State 3.6High level output current, (IOH) 1.4 V to 1.6 V -2 mA 1.65 V to 1.95 V -4 2.3 V to 2.7 V -8 3 V to 3.6 V -12 Low level output current, (IOL) 1.4 V to 1.6 V 2
22、 mA 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 12 Input transition rise or fall rate,(t/v) 5 ns/V Operating free air temperature, (TA) -55 125 C _ 11/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor m
23、aintain no responsibility or liability for product used beyond the stated limits. 12/ VCCI is the VCCassociated with the input port. 13/ VCCO is the VCCassociated with the output port. 14/ All unused data inputs of the device must held at VCCIor GND to ensure proper device operation. Refer to manufa
24、cturer data, Implications of Slow or Floating CMOS inputs, literature number SCBA004. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 5 2. APPLICABLE DOCUMENT
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