DLA DSCC-VID-V62 12631-2012 MICROCIRCUIT LINEAR LOW VOLTAGE 1 15 V TO 5 5 V 4-CHANNEL BIDIRECTIONAL LOGIC LEVEL TRANSLATOR MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original d
2、ate of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, LOW VOLTAGE, 1.15 V TO 5.5 V, 4-CHANNEL, BIDIRECTIONAL LOGIC LEVEL TRANSLATOR, MONOLITHIC SILICON 12-10-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12631 REV PAGE 1 OF 11 AMSC N/A 5962-V009-13 Pro
3、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12631 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage, 1.15 V t
4、o 5.5 V, 4-channel bidirectional logic level translator microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number
5、 for identifying the item on the engineering documentation: V62/12631 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG3304-EP Low voltage, 1.15 V to 5.5 V, 4-channel bidirectional logic
6、level translator 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MO-153-AB-1 Thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the
7、 device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 1623
8、6 DWG NO. V62/12631 REV PAGE 3 1.3 Absolute maximum ratings. 1/ VCCAto GND -0.3 V to +7.0 V VCCYto GND VCCAto +7.0 V Digital inputs (A) -0.3 V to (VCCA+ 0.3 V) Digital inputs (Y) -0.3 V to (VCCY+ 0.3 V) EN to GND -0.3 V to +7.0 V Operating temperature range -55C to +125C Storage temperature range .
9、-65C to 150C Junction temperature 150C JAThermal impedance (4 layer board) , Case outline X . 112.6C/W Lead temperature, soldering: Vapor phase (60 sec) 215C Infrared (15 sec) . 220C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for S
10、emiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers pa
11、rt number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical char
12、acteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 1/ Stresses beyond those l
13、isted under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated c
14、onditions for extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12631 REV PAGE 4 3.5 Diagrams. 3.5.1 Case outline. The case out
15、line shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block dia
16、gram. The functional block diagram shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12631 REV PAGE 5 TABLE I. Electrical performance characteri
17、stics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ 3/ Max LOGIC INPUTS/OUTPUTS A side Input high voltage 4/ VIHAVCCA= 1.2 V + 0.1 V/-0.05 V VCCAx 0.88 V VCCA= 1.8 V 0.15 V VCCAx 0.72 VCCA= 2.5 V 0.2 V 1.7 VCCA= 3.3 V 0.3 V 2.2 VCCA= 5 V 0.5 V VCCAx 0.7 Input low voltage 4/ VILAVCCA= 1.2 V
18、+ 0.1 V/-0.05 V VCCAx 0.35 VCCA= 1.8 V 0.15 V VCCAx 0.35 VCCA= 2.5 V 0.2 V 0.7 VCCA= 3.3 V 0.3 V 0.8 VCCA= 5 V 0.5 V VCCAx 0.30 Output high voltage VOHAVY= VCCY, IOH= 20 A VCCA 0.4 Output low voltage VOLAVY= 0 V, IOL= 20 A 0.4 Capacitance 4/ CAf = 1 MHz, EN = 0 9 pF Leakage current ILA, HI-ZVA= 0 V/
19、VCCA, EN = 0 1 A Y side Input high voltage 4/ VIHYVCCY= 1.8 V 0.15 V VCCYx 0.67 V VCCY= 2.5 V 0.2 V 1.7 VCCY= 3.3 V 0.3 V 2 VCCY= 5 V 0.5 V VCCYx 0.7 Input low voltage 4/ VILYVCCY= 1.8 V 0.15 V VCCYx 0.35 VCCY= 2.5 V 0.2 V 0.7 VCCY= 3.3 V 0.3 V 0.8 VCCY= 5 V 0.5 V VCCYx 0.25 Output high voltage VOHY
20、VA= VCCA, IOH= 20 A VCCY- 0.4 Output low voltage VOLYVA= 0 V, IOL= 20 A 0.4 Capacitance 3/ CYf = 1 MHz, EN = 0 6 pF Leakage current ILY, HI-ZVY= 0 V/VCCY, EN = 0 1 A Enable (EN) Input high voltage 4/ VIHAVCCA= 1.2 V + 0.1 V/-0.05 V VCCAx 0.88 VCCA= 1.8 V 0.15 V VCCAx 0.72 VCCA= 2.5 V 0.2 V 1.7 VCCA=
21、 3.3 V 0.3 V 2.2 VCCA= 5 V 0.5 V VCCAx 0.7 Input low voltage 4/ VILAVCCA= 1.2 V + 0.1 V/-0.05 V VCCAx 0.35 VCCA= 1.8 V 0.15 V VCCAx 0.35 VCCA= 2.5 V 0.2 V 0.7 VCCA= 3.3 V 0.3 V 0.8 VCCA= 5 V 0.5 V VCCAx 0.30 Leakage current ILEN1 A Capacitance 3/ CEN3 pF Enable time 4/ tENRS= RT= 50 , VA= 0 V/VCCA(A
22、 Y), VY= 0 V/VCCY(Y A) 1 1.8 s See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12631 REV PAGE 6 TABLE I. Electrical performance characteristics
23、 - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ 3/ Max SWITCHING CHARACTERISTICS 4/ 3.3 V 0.3 V VCCA VCCY, VCCY= 5 V 0.5 V A Y level tran slation Propagation delay Rise time Fall time Maximum data rate Channel to channel skew Part to part skew tP, AY tR, AY tF, AY DMAX, AY tSKEW,
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