DLA DSCC-VID-V62 09601-2009 MICROCIRCUIT DIGITAL MIXED SIGNAL MICROCONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENS

2、E SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICROCONTROLLER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09601 09-04-07 REV PAGE 1 OF 40 AMSC N/A 59

3、62-V054-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performan

4、ce mixed signal microcontroller microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the ite

5、m on the engineering documentation: V62/09601 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430F249-EP Mixed signal microcontroller 1.2.2 Case outline(s). The case outlines are as spec

6、ified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 64 JEDEC MO-220 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C G

7、old plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS-0.3 V to 4.1 V Voltage applied to any pin . -0.3 V to VCC+ 0.3 V 2/ Diode current at any device terminal . 2 mA Storage temperature range, TSTG(unprogrammed device) -55C to 150C 3/ Stor

8、age temperature range, TSTG(programmed device) -55C to 125C 3/ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated unde

9、r “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltages referenced to VSS. The JTAG fuse blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the T

10、DI/TCLK pin when blowing the JTAG fuse. 3/ Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Provided by IHSNot for Resal

11、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 3 1.4 Recommended operating conditions. 4/ Supply voltage during program execution (VCC) (AVCC= DVCC= VCC) . 1.8 V to 3.6 V 5/ S

12、upply voltage during flash memory programming (VCC) (AVCC= DVCC= VCC) . 2.2 V to 3.6 V 5/ Supply voltage (VSS) (AVSS= DVSS= VSS) 0 V Processor frequency fSYSTEM(Maximum MCLK frequency): 6/ 7/ 8/ VCC= 1.8 V, Duty Cycle 50% 10% 4.15 MHz VCC= 2.7 V, Duty Cycle 50% 10% 12 MHz VCC 3.3 V, Duty Cycle 50% 1

13、0% 16 MHz Flash temperature range: Read . -55C to 125C Write . -55C to 125C Operating free air temperature range, TA. -55C to 125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity

14、classification for nonhermetic solid state surface mount devices. (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly

15、marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applic

16、able) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specif

17、ied herein. _ 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ It is recommended to power AVCCand DVCCfrom the same so

18、urce. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up. 6/ The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 7/ Modules might have a different maximum input clock s

19、pecification. Refer to the data sheet from manufacturer. 8/ See figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 4 3.5 Diagrams. 3.5.1 Case

20、 outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Operating area. The operating area shall be as sho

21、wn in figure 4. 3.5.5 Active mode supply current. The active mode supply current shall be as shown in figure 5. 3.5.6 POR/Brownout reset. The POR/Brownout reset shall be as shown in figure 6-8. 3.5.7 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure

22、 9-15. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions 2/ unless

23、 otherwise specified TAVCCMin Max Unit Active mode supply current (into DVCC+ AVCC) Excluding External current 3/ 4/ -55C to 105C 275 TYP 125C 2.2 V 318 -55C to 105C 386 TYP Active mode (AM) current (1 MHz) IAM, 1MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32,768 Hz, Program executes from flash, BCSCTL1 =

24、 CALBC1_1MHz, DCOCTL = CALDCO_1 MHz CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 125C 3 V 449 A -55C to 105C 230 TYP 125C 2.2 V 267 -55C to 105C 321 TYP Active mode (AM) current (1 MHz) IAM, 1MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32,768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALD

25、CO_1 MHz CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 125C 3 V 370 A -55C to 105C 1.5 TYP 125C 2.2 V 10.5 -55C to 105C 2 TYP Active mode (AM) current (4 kHz) IAM, 4kHzfMCLK= fSMCLK= fACLK= 32,768 Hz/8 = 4096 Hz, fDCO= 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, C

26、PUOFF = 0, SCGO = 0, SCG1 = 0, OSCOFF = 0 125C 3 V 12.2 A -55C to 105C 55 TYP 125C 2.2 V 81 -55C to 105C 67 TYP Active mode (AM) current (100 kHz) IAM, 100 kHzfMCLK= fSMCLK= fDCO(0,0) 100 kHz, fACLK= 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCGO = 0, SCG1 = 0, OSCOFF = 1 125

27、C 3 V 100 A -55C to 105C 60 TYP 125C 2.2 V 88 -55C to 105C 75 TYP Low power mode 0, (LPM0) current 5/ ILPM0, 1 MHzfMCLK= 0 MHz, fSMCLK= fDCO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1 MHz, DCOCTL = CALDCO_1 MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 125C 3 V 98 A -55C to 105C 33 TYP 125C 2.2

28、V 45 -55C to 105C 36 TYP Low power mode 0, (LPM0) current 5/ ILPM0, 100 kHzfMCLK= 0 MHz, fSMCLK= fDCO(0,0) 100 kHz, fACLK= 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCGO = 0, SCG1 = 0, OSCOFF = 1 125C 3 V 50 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking per

29、mitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Limits Test Symbol Conditions 2/ unless otherwise specified TAVCCMin Max Unit Active mode supply c

30、urrent (into DVCC+ AVCC) Excluding External current - Continued 3/ 4/ -55C to 105C 20 TYP 125C 2.2 V 42 -55C to 105C 23 TYP Low power mode 2 (LPM2) current 6/ ILPM2fMCLK= fSMCLK= 0 MHz, fDCO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1 MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOF

31、F = 0 125C 3 V 48 A -55C 0.8 TYP 25C 1.3 105C 15 125C 2.2 V 22 -55C 0.9 TYP 25C 1.4 105C 17 Low power mode 3 (LPM3) current 6/ ILPM3, LFXT1fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 32,768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 125C 3 V 27 A -55C 0.3 TYP 25C 0.9 105C 4.5 125C 2.2 V 15 -55C 0.4 TYP 2

32、5C 1 105C 5.5 Low power mode 3 current (LPM3) 6/ ILPM3, VLOfDCO= fMCLK= fSMCLK= 0 MHz, fACLK= from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 125C 3 V 16 A -55C 0.1 TYP 25C 0.5 105C 13 Low power mode 4 current (LPM4) 7/ ILPM4fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 0 Hz, CPUO

33、FF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 125C 2.2 V/ 3 V 22 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 7 TABLE I

34、. Electrical performance characteristics Continued. 1/ Limits Test Symbol Conditions -55C TA 125C 2/ unless otherwise specified VCCMin Max Unit Schmitt-trigger inputs ports P1, P2, P3, P4, P5, P6, RST/RST , JTAG, XIN, and XT2IN) 8/ 0.45 VCC0.75 VCC2.2 V 1 1.65 Positive going input threshold voltage

35、VIT+3 V 1.35 2.25 V 0.25 VCC0.55VCC2.2 V 0.55 1.2 Negative going input threshold voltage VIT-3 V 0.75 1.65 V 2.2 V 0.2 1 Input voltage hysteresis (VIT+ - VIT-) Vhys3 V 0.3 1 V Pullup/Pulldown resistor RPullPullup: VIN= VSS; Pulldown: VIN= VCC20 50 k Input capacitance CIVIN= VSSor VCC5 TYP pFInputs p

36、orts P1 and P2 External interrupt timing t(int)Port P1, P2: P1.x to P2.x, external trigger pulse width to set interrupt flag 9/ 2.2 V/ 3 V 20 TA0, TA1, TA2 2.2 V 62 Timer_A, Timer_B capture timing tcapTB0, TB1, TB2, TB3, TB4, TB5, TB6 3 V 50 ns fTAext2.2 V 8 Timer_A, Timer_B clock frequency external

37、ly applied to pin fTBextTACLK, TBCLK, INCLK: t(H)= t(L)3 V 10 fTAint2.2 Timer_A, Timer_B clock frequency fTBintSNCLK or ACLK signal selected 3 V 10 MHz Leakage current ports P1, P2, P3, P4, P5, and P6 High impedance leakage current Ilkg(Px.x)10/ 11/ 2.2 V/ 3 V 50 nA Standard inputs - RST /NMI Low le

38、vel input voltage VILVSSVSS + 0.6 High level input voltage VIH2.2 V/ 3 V 0.8VCCVCCV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/

39、09601 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Limits Test Symbol Conditions 2/ -55C TA 125C unless otherwise specified VCCMin Max Unit Outputs ports P1, P2, P3, P4, P5, and P6 IOH(max) = -1.5 mA 12/ VCC 0.25 VCCIOH(max) = -6 mA 13/ 2.2 V VCC 0.6 VCCIOH(max) = -1.5 mA

40、 12/ VCC 0.25 VCCHigh level output voltage VOHIOH(max) = -6 mA 13/ 3 V VCC 0.6 VCCV IOL(max) = 1.5 mA 12/ VSSVSS+ 0.25 IOL(max) = 6 mA 13/ 2.2 V VSSVSS+ 0.6 IOL(max) = 1.5 mA 12/ VSSVSS+ 0.25 Low level output voltage VOLIOL(max) = 6 mA 13/ 3 V VSSVSS+ 0.6 V Output frequency ports P1, P2, P3, P4, P5,

41、 and P6 2.2 V DC 10 Port output frequency (with load) fPx.yP1.4/SMCLK, CL= 20 pF, RL= 1 k 14/ 15/ 3 V DC 12 MHz 2.2 V DC 12 Clock output frequency fPort_CLKP2.0/ACLK/CA2, P1.4/SCMCLK, CL = 20 pF, RL= 1 k 15/ 3 V DC 16 MHz P1.0/TACLK/CAOUT, CL= 20 pF, LF mode 30 P1.0/TACLK/CAOUT, CL= 20 pF, XT1 mode

42、40 P1.0/TA0, CL= 20 pF, XT1 mode 40 % P1.0/TA0, CL= 20 pF, DCO 50% - 15 ns 50% + 15 ns P1.4/SMCLK, CL= 20 pF, XT2 MODE 40 60 % Duty cycle of output frequency t(Xdc)P1.4/SMCLK, CL= 20 pF, DCO 50% - 15 ns 50% + 15 ns POR/brownout reset (BOR) 16/ 17/ Operating voltage VCC(start)dVCC/dt 3 V/s See figure

43、 6 0.7 x V(B_IT-)TYP V Negative going VCCreset threshold voltage V(B_IT-)dVCC/dt 3 V/s See figure 6-8 1.71 V VCCreset threshold hysteresis Vhys(B_IT-)dVCC/dt 3 V/s See figure 6 70 210 mV BOR reset release delay time td(BOR)See figure 6 2000 s Pulse length needed at RST /NMI pin to accepted reset int

44、ernally t(reset)2.2 V/ 3V 2 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09601 REV PAGE 9 TABLE I. Electrical performance chara

45、cteristics Continued. 1/ Limits Test Symbol Conditions 2/ -55C TA 125C unless otherwise specified Min Max Unit SVS (supply voltage supervisor/monitor) dVCC/dt 30 V/ms See figure 9 5 150 t(SVSR)dVCC/dt 30 V/ms 2000 d(SVSon)SVSON, switch from VLD = 0 to VLD 0, VCC= 3 V 20 150 settleVLD 0 19/ 12 s V(SV

46、Sstart)VLD 0, VCC/dt 3 V/s See figure 9 1.7 V VLD = 1 70 210 mV dVCC/dt 3 V/s See figure 9 VLD = 2 to 14 0.001 x V(SVS_IT-)0.016 x V(SVS_IT-)Vhys(SVS_IT-)dVCC/dt 3 V/s, External voltage applied on A7, See figure 9 VLD = 15 4.4 20 mV VLD = 1 1.8 2.05 VLD = 2 1.94 2.25 VLD = 3 2.05 2.37 VLD = 4 2.14 2

47、.48 VLD = 5 2.24 2.60 VLD = 6 2.33 2.71 VLD = 7 2.46 2.86 VLD = 8 2.58 3.00 VLD = 9 2.69 3.13 VLD = 10 2.83 3.29 VLD = 11 2.94 3.42 VLD = 12 3.11 3.61 18/ VLD = 13 3.24 3.76 18/ dVCC/dt 3 V/s See figure 9-10 VLD = 14 3.43 3.99 18/ V(SVS_IT-)dVCC/dt 3 V/s, External voltage applied on A7, See figure 9-10 VLD = 15 1.1 1.3 V ICC(SVS)20/ VLD 0, VCC= 2.2 V/3 V 15 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM