DLA DSCC-VID-V62 08619-2008 MICROCIRCUIT LINEAR 24 V LOW DROPOUT REGULATOR MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKE
2、D BY RAJESH PITHADIA APPROVED BY ROBERT M. HEBER TITLE MICROCIRCUIT, LINEAR, 24 V, LOW DROPOUT REGULATOR, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08619 08-10-15 REV PAGE 1 OF 10 AMSC N/A 5962-V002-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without lic
3、ense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 24 V low dropout regulator microcircuit, with an operating temperature range of -55C to
4、+125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/08619 - 01 X E Drawing Device type Case outline Lead
5、finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS71501-EP 24 V low dropout regulator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 MO-203-AA Plastic su
6、rface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or
7、 networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08619 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Input voltage range (VIN) -0.3 V to 24 V Output voltage range (VOUT) . -0.3 V to 6 V Peak output current Inte
8、rnally limited Continuous total power dissipation (PD) . See 1.5 dissipation rating table Junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) -65C to +150C Electrostatic discharge (ESD) rating: Human body model (HDM) . 2000 V Charge device model (CDM) 500 V 1.4 Recommended
9、 operating conditions. 3/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Dissipation rating table. Board JCJADerating factor above TA 25C TA= 70C TA= 85C TA= 25C power rating power rating power rating Low K 4/ 165C/W 395C/W 2.52 mWC 250 mW 140 mW 100 mW High K 5/ 165C/W 315C/W 3.18 mW
10、/C 320 mW 175 mW 130 mW 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
11、not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are within respect to the network ground terminal. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The man
12、ufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board. 5/ The JEDEC High K (2s2p) board design
13、 used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS
14、COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08619 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834
15、or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. T
16、he unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design,
17、 construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Bloc
18、k diagram. The block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08619 REV PAGE 5 TABLE I. Electrical performance charac
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