DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(11页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct pin name 24 in terminal connection table, figure 4. - PHN 11-09-12 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawi
2、ng REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.
3、3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY MM DD 06-08-16 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06654 REV A PAGE 1 OF 1 AMSC N/A 5962-V082-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
4、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit transparent D-type latch with 3-state outputs microcircuit, with an operatin
5、g temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06654 - 01 X E Drawing
6、 Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH162373-EP 3.3-V ABT 16-bit transparent D-type latch with 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline
7、letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-118 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium
8、E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.
9、5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 30 mA Curre
10、nt into any output in the high state (IO) . 30 mA 3/ Input clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overa
11、ll device life. 6/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/066
12、54 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th St
13、reet, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit contai
14、ner. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 D
15、esign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diag
16、ram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or netw
17、orking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIK
18、II= -18 Ma 2.7 V 25C, -55C to +125C All -1.2 V High level output voltage VOHIOH= -12 Ma 3 V 2 V Low level output voltage VOLIOL= 12 Ma 3 V 0.8 V Input current IIControl inputs VI= 5.5 V 0 V or 3.6 V 10 A Control inputs VI= VCCor GND 3.6 V 1 Data inputs, VI= VCC3.6 V 1 Data inputs, VI= 0 V 3.6 V -5 I
19、nput current (hold) II(hold)Data inputs, VI= 0.8 V 3 V 75 A Data inputs, VI= 2.0 V 3 V -75 3-state output current, high IOZHVO= 3 V 3.6 V 5 A 3-state output current, low IOZLVO= 0.5 V 3.6 V -5 A 3-state output current, power-up IOZPU2/ VO= 0.5 V to 3 V, OE= dont care 0 V to 1.5 V 100 A 3-state outpu
20、t current, power-down IOZPD2/ VO= 0.5 V to 3 V, OE= dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high IO= 0, VI= VCCor GND 3.6 V 0.19 mA Outputs low IO= 0, VI= VCCor GND 3.6 V 5 Outputs disabled IO= 0, VI= VCCor GND 3.6 V 0.19 Quiescent supply current delta ICC3/ One input at VCC
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- DLADSCCVIDV6206654REVA2011MICROCIRCUITDIGITALADVANCEDBIPOLARCMOS33VABT16BITTRANSPARENTDTYPELATCHWITH3STATEOUTPUTSMONOLITHICSILICONPDF

链接地址:http://www.mydoc123.com/p-689235.html