欢迎来到麦多课文档分享! | 帮助中心 海量文档,免费浏览,给你所需,享你所想!
麦多课文档分享
全部分类
  • 标准规范>
  • 教学课件>
  • 考试资料>
  • 办公文档>
  • 学术论文>
  • 行业资料>
  • 易语言源码>
  • ImageVerifierCode 换一换
    首页 麦多课文档分享 > 资源分类 > PDF文档下载
    分享到微信 分享到微博 分享到QQ空间

    DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

    • 资源ID:689235       资源大小:194.60KB        全文页数:11页
    • 资源格式: PDF        下载积分:10000积分
    快捷下载 游客一键下载
    账号登录下载
    微信登录下载
    二维码
    微信扫一扫登录
    下载资源需要10000积分(如需开发票,请勿充值!)
    邮箱/手机:
    温馨提示:
    如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
    如需开发票,请勿充值!如填写123,账号就是123,密码也是123。
    支付方式: 支付宝扫码支付    微信扫码支付   
    验证码:   换一换

    加入VIP,交流精品资源
     
    账号:
    密码:
    验证码:   换一换
      忘记密码?
        
    友情提示
    2、PDF文件下载后,可能会被浏览器默认打开,此种情况可以点击浏览器菜单,保存网页到桌面,就可以正常下载了。
    3、本站不支持迅雷下载,请使用电脑自带的IE浏览器,或者360浏览器、谷歌浏览器下载即可。
    4、本站资源下载后的文档和图纸-无水印,预览文档经过压缩,下载后原文更清晰。
    5、试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。

    DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct pin name 24 in terminal connection table, figure 4. - PHN 11-09-12 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawi

    2、ng REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.

    3、3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY MM DD 06-08-16 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06654 REV A PAGE 1 OF 1 AMSC N/A 5962-V082-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

    4、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit transparent D-type latch with 3-state outputs microcircuit, with an operatin

    5、g temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06654 - 01 X E Drawing

    6、 Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH162373-EP 3.3-V ABT 16-bit transparent D-type latch with 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline

    7、letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-118 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium

    8、E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.

    9、5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 30 mA Curre

    10、nt into any output in the high state (IO) . 30 mA 3/ Input clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overa

    11、ll device life. 6/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/066

    12、54 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th St

    13、reet, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit contai

    14、ner. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 D

    15、esign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diag

    16、ram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or netw

    17、orking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIK

    18、II= -18 Ma 2.7 V 25C, -55C to +125C All -1.2 V High level output voltage VOHIOH= -12 Ma 3 V 2 V Low level output voltage VOLIOL= 12 Ma 3 V 0.8 V Input current IIControl inputs VI= 5.5 V 0 V or 3.6 V 10 A Control inputs VI= VCCor GND 3.6 V 1 Data inputs, VI= VCC3.6 V 1 Data inputs, VI= 0 V 3.6 V -5 I

    19、nput current (hold) II(hold)Data inputs, VI= 0.8 V 3 V 75 A Data inputs, VI= 2.0 V 3 V -75 3-state output current, high IOZHVO= 3 V 3.6 V 5 A 3-state output current, low IOZLVO= 0.5 V 3.6 V -5 A 3-state output current, power-up IOZPU2/ VO= 0.5 V to 3 V, OE= dont care 0 V to 1.5 V 100 A 3-state outpu

    20、t current, power-down IOZPD2/ VO= 0.5 V to 3 V, OE= dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high IO= 0, VI= VCCor GND 3.6 V 0.19 mA Outputs low IO= 0, VI= VCCor GND 3.6 V 5 Outputs disabled IO= 0, VI= VCCor GND 3.6 V 0.19 Quiescent supply current delta ICC3/ One input at VCC

    21、 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 3 TYP pF Output capacitance CoVO= 3 V or 0 V 3.3 V 9 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

    22、CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Pulse duration, LE high twSee figure 5. 2.7 V 25C, -55C to +125C All 3 n

    23、s 3.3 V 0.3 V 3 Setup time, data before LE tsuSee figure 5. 2.7 V 0.6 ns 3.3 V 0.3 V 1.3 Hold time, data after LE thSee figure 5. 2.7 V 1.1 ns 3.3 V 0.3 V 1 Propagation delay time, D to Q tPLHCL= 50 pF See figure 5. 2.7 V 5.7 ns 3.3 V 0.3 V 1.8 5 tPHL2.7 V 4.8 3.3 V 0.3 V 1.8 4.4 Propagation delay t

    24、ime, LE to Q tPLHCL= 50 pF See figure 5. 2.7 V 6.2 ns 3.3 V 0.3 V 2.1 5.4 tPHL2.7 V 4.7 3.3 V 0.3 V 2.1 4.9 Propagation delay time, output enable, OEto Q tPZHCL= 50 pF See figure 5. 2.7 V 7 ns 3.3 V 0.3 V 1.7 5.6 tPZL2.7 V 5.9 3.3 V 0.3 V 1.7 5.3 Propagation delay time, output disable, OEto Q tPHZCL

    25、= 50 pF See figure 5. 2.7 V 6.6 ns 3.3 V 0.3 V 2.3 6.3 tPLZ2.7 V 6.4 3.3 V 0.3 V 1 7.4 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full tem

    26、perature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ On products compliant to MIL-PRF-38535, this parameter is not production tested. 3/ This is the increase in supply curr

    27、ent for each input that is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 7 Case X Dim

    28、ensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A - 0.110 - 2.79 E 0.395 0.420 10.03 10.67 A1 0.008 - 0.20 - E1 0.291 0.299 7.39 7.59 b 0.008 0.014 0.20 0.34 e 0.025 BSC 0.635 BSC c 0.005 0.010 0.13 0.25 L 0.020 0.040 0.51 1.02 D 0.620 0.630 15.75 16.00 NO

    29、TES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MO-118. 3. All linear dimensions are in inches (millimeters). Millimeters equivalents are shown for general information only. 4. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mi

    30、llimeters). FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 8 Inputs Output OELE D Q L H H H L H L L L L X Q0H X X Z H =

    31、High voltage level X = Irrelevant L = Low voltage level Z = High Impedance state Q0= Level of Q before the indicated steady-state input conditions were established. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

    32、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1OE25 2LE 2 1Q1 26 2D8 3 1Q2 27 2D7 4 GND 28 GND 5 1Q3 29 2D6 6 1Q4 30 2D5 7 VCC31 VCC8

    33、 1Q5 32 2D4 9 1Q6 33 2D3 10 GND 34 GND 11 1Q7 35 2D2 12 1Q8 36 2D1 13 2Q1 37 1D8 14 2Q2 38 1D7 15 GND 39 GND 16 2Q3 40 1D6 17 2Q4 41 1D5 18 VCC42 VCC19 2Q5 43 1D4 20 2Q6 44 1D3 21 GND 45 GND 22 2Q7 46 1D2 23 2Q8 47 1D1 24 2OE48 1LE FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo repr

    34、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06654 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low

    35、, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns.

    36、 4. The outputs are measured one at a time, with one transition per measurement. FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D

    37、WG NO. V62/06654 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, clas

    38、sification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NO

    39、TES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes witho

    40、ut notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administr

    41、ative control number 1/ Device manufacturer CAGE code Vendor part number Top-side marking V62/06654-01XE 01295 CLVTH162373MDLREP LVTH162373EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-


    注意事项

    本文(DLA DSCC-VID-V62 06654 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf)为本站会员(rimleave225)主动上传,麦多课文档分享仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文档分享(点击联系客服),我们立即给予删除!




    关于我们 - 网站声明 - 网站地图 - 资源地图 - 友情链接 - 网站客服 - 联系我们

    copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
    备案/许可证编号:苏ICP备17064731号-1 

    收起
    展开