DLA DSCC-VID-V62 05610 REV B-2012 MICROCIRCUIT LINEAR LOW NOISE HIGH SLEW RATE UNITY GAIN STABLE VOLTAGE FEEDBACK AMPLIFIER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add “Maximum junction temperature to prevent oscillation, (TJ)” in section 1.3. - PHN 10-06-22 Thomas M. Hess B Under paragraph 1.3, ESD rating Machine model limit, delete +100 V and substitute “+1000 V”. Add footnote to paragraphs 1.2.2, 1.4, and 6.3. Make

2、 changes to dual and single supply voltage limits under paragraph 1.4. Table I, VS= 5.0 V condition, delete Rf = 301 and replace with Rf = 249 , make changes to common mode rejection ratio, output current (sinking), specified operating voltage, positive and negative power supply rejection tests. Tab

3、le I, VS= 5.0 V condition, delete Rf = 301 and replace with Rf = 249 , make changes to output current (sourcing and sinking), common mode rejection ratio, positive and negative power supply rejection tests. Make corrections to A1 and c dimensions under case X. Make corrections to all dimensions unde

4、r case Y. Update notes for case outlines X and Y under figure 1. - ro 12-06-14 Charles F. Saffle CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF P

5、AGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE VOLTAGE FEE

6、DBACK AMPLIFIER, MONOLITHIC SILICON 05-06-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05610 REV B PAGE 1 OF 12 AMSC N/A 5962-V019-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

7、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low noise, high slew rate, unity gain stable voltage feedback amplifier, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Dra

8、wing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05610 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1)

9、(See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 THS4271-EP Low noise, high slew rate, unity gain stable voltage feedback amplifier 02 THS4275-EP Low noise, high slew rate, unity gain stable voltage feedback amplifier 1.2.2 Case outline(s). The case outline(s)

10、 are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 JEDEC MS-012 Plastic small outline package Y 2/ 8 JEDEC M0-187 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufactu

11、re: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other _ 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ The manufacture has changed lead frames NiPdAu to NiPd

12、AuAg and location of assembly from their Hana facility to their Shanghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a NiPdAu frame from the Hana facility. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C

13、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 3 1.3 Absolute maximum ratings. 3/ Supply voltage, (VS) +16.5 V Input voltage, (VI): VSOutput current, (IO) 100 mA Continuous power dissipation . See package dissipation rating table Maximum junction temperature, (TJ) .

14、+150C Maximum junction temperature, continuous operation, long term reliability, (TJ) +125C 4/ Maximum junction temperature to prevent oscillation, (TJ) +60C 5/ Storage temperature range, (TSTG) -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds +300C ESD ratings: Human body

15、model (HBM) +3000 V Charge device model (CDM) . +1500 V Machine model (MM) +1000 V Package dissipation ratings: Package JC(C/W) JA 6/ (C/W) Case X 38.3 97.5 Case Y 7/ 4.7 58.4 1.4 Recommended operating conditions. 8/ Supply voltage, (VS+and VS-): Dual supply . 2.5 V to 5 V Single supply . +5.0 V to

16、+10 V Input common mode voltage range, . VS-+ 1.4 V to VS+- 1.4 V Operating free air temperature range, (TA) . -55C to +125C 3/ The absolute maximum temperature under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure

17、 to absolute maximum conditions for extended periods may affect device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 4/ Long term high temperature storage and/or extended used at maximum reco

18、mmended operating conditions may result in a reduction of overall device life. See figure 3 for additional information on thermal derating. 5/ Device type 01 may have low-level oscillation when the die temperature exceeds +60C and is not recommended for new design. See maximum die temperature to pre

19、vent oscillation in manufacturer data. 6/ This data was taken using the JEDEC standard high K test PCB. 7/ The devices on this drawing may incorporate a thermal pad on the underside of the chip. This act as a heatsink and must be connected to a thermally dissipative plane for proper power dissipatio

20、n. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. Refer to the manufacturer for more information about utilizing the thermally enhanced package. 8/ Use of this product beyond the manufacturers design rules or stated parameters is

21、done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE

22、IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA

23、 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit

24、container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein.

25、 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure

26、 2. 3.5.3 Wirebond life versus temperature. Wirebond life versus temperature shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 R

27、EV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Test condition VS= 5.0 V, G = +2 Rf = 249 , RL= 499 unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C AC Performance Small signal bandwidth G = 1, VO= 100 mVPP, RL= 150 1.4

28、 GHz Typ G = -1, VO= 100 mVPP400 MHz G = 2, VO= 100 mVPP390 G = 5, VO= 100 mVPP85 G = 10, VO= 100 mVPP40 0.1 dB flat bandwidth G = 1, VO= 100 mVPP, RL= 150 200 Gain bandwidth product G 10, f = 1 MHz 400 Full power bandwidth G = -1, VO= 2 VP80 Slew rate G = 1, VO= 2 V Step 950 V/s G = -1, VO= 2 V Ste

29、p 1000 Setting time to 0.1% G = -1, VO= 4 V Step 25 ns Setting time to 0.01% G = -1, VO= 4 V Step 38 Harmonic distortion G= 1, VO= 1 VPP, f = 30 MHz 2ndharmonic distortion RL= 150 -92 dBc RL= 499 -80 3rdharmonic distortion RL= 150 -95 RL= 499 -95 Harmonic distortion G = 2, VO= 2 VPP, f = 30 MHz 2ndh

30、armonic distortion RL= 150 -65 dBc RL= 499 -70 3rdharmonic distortion RL= 150 -80 RL= 499 -90 Third order intermodulation (IMD3) G = 2, VO= 2 VPP, RL= 150 , f = 70 MHz -60 Third order output intercept (OIP3) G = 2, VO= 2 VPP, RL= 150 , f = 70 MHz 35 dBm Differential gain (NTSC, PAL) G = 2, RL= 150 0

31、.007% Differential phase (NTSC, PAL) G = 2, RL= 150 0.004 degrees Input voltage noise f = 1 MHz 3 nV/ Hz Input current noise f = 1 MHz 3 pA/ Hz DC performance Open loop voltage gain (AOL) VO= 50 mV, RL= 499 75 65 56 dB Min Input offset voltage VCM= 0 V 5 14 16 mV Max Average offset voltage drift 10

32、V/C Typ Input bias current 6 15 18 A Max Average bias current drift 10 nA/C Typ Input offset current 1 6 8 A Max Average offset current drift 10 nA/C Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER

33、, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 6 TABLE I. Electrical performance characteristics Continued. Test Test condition VS= 5.0 V, G = +2 Rf = 249 , RL= 499 unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C

34、 to +125C Input characteristics Common mode input range 4.0 3.6 3.5 V Min Common mode rejection ratio VICM= 2 V 72 67 62 dB Min Input resistance Common mode 5 M Typ Input capacitance Common mode / differential 0.4/0.8 pF Typ Output characteristics Output voltage swing G = +2 4 3.75 3.6 V Min Output

35、current (sourcing) RL= 10 160 120 104 mA Min Output current (sinking) RL= 10 80 60 44 mA Min Output impedance f = 1 MHz 0.1 Typ Power supply Specified operating voltage 5 5 5 V Max Maximum quiescent current 22 24 34 mA Max Minimum quiescent current 22 20 13 mA Min Power supply rejection (+PSRR) VS+=

36、 5.5 V to 4.5 V, VS-= 5 V 85 75 58 dB Min Power supply rejection (-PSRR) VS+= 5 V, VS-= -5.5 V to -4.5 V 75 65 57 dB Min Power down characteristics (device type 02 only) Power down voltage level 2/ REF = 0 V, or VS-Enable REF + 1.8 V Min Power down REF + 1 Max REF = VS+ or floating Enable REF -1 Min

37、 Power down REF 1.7 Max Power down quiescent current PD = Ref + 1 V, Ref = 0 V 875 1000 1200 A Max PD = Ref -1.7 V, Ref = VS+650 800 1000 A Max Turn on time delay (t(ON) 50% of final supply current value 4 s Typ Turn off time delay (t(OFF) 50% of final supply current value 3 s Typ Input impedance f

38、= 1 MHz 4 G Typ Output impedance 200 k Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 7 TABLE I. Electrical perfor

39、mance characteristics Continued. Test Test condition VS= 5.0 V, G = +2 Rf = 249 , RL= 499 unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C AC Performance Small signal bandwidth G = 1, VO= 100 mVPP, RL= 150 1.2 GHz Typ G = -1, VO= 100 mVPP38

40、0 MHz G = 2, VO= 100 mVPP360 G = 5, VO= 100 mVPP80 G = 10, VO= 100 mVPP35 0.1 dB flat bandwidth G = 1, VO= 100 mVPP, RL= 150 120 Gain bandwidth product G 10, f = 1 MHz 350 Full power bandwidth G = -1, VO= 2 VP60 Slew rate G = 1, VO= 2 V Step 700 V/s G = -1, VO= 2 V Step 750 Setting time to 0.1% G =

41、-1, VO= 2 V Step 18 ns Setting time to 0.01% G = -1, VO= 2 V Step 66 Harmonic distortion G= 1, VO= 1 VPP, f = 30 MHz 2ndharmonic distortion RL= 150 75 dBc RL= 499 72 3rdharmonic distortion RL= 150 -70 RL= 499 -70 Third order intermodulation (IMD3) G = 2, VO= 1 VPP, RL= 150 , f = 70 MHz -65 Third ord

42、er output intercept (OIP3) G = 2, VO= 1 VPP, RL= 150 , f = 70 MHz 32 dBm Input voltage noise f = 1 MHz 3 nV/ Hz Input current noise f = 10 MHz 3 pA/ Hz DC performance Open loop voltage gain (AOL) VO= 50 mV, RL= 499 68 63 56 dB Min Input offset voltage VCM= VS/2 5 14 16 mV Max Average offset voltage

43、drift 10 V/C Typ Input bias current 6 15 18 A Max Average bias current drift 10 nA/C Typ Input offset current 1 6 8 A Max Average offset current drift 10 nA/C Typ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPP

44、LY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05610 REV B PAGE 8 TABLE I. Electrical performance characteristics Continued. Test Test condition VS= 5.0 V, G = +2 Rf = 249 , RL= 499 unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C

45、 25C -55C to +125C Input characteristics Common mode input range 1/4 1.3/3.7 1.5/3.5 V Min Common mode rejection ratio VCM= 0.5 V, VO= 2.5 V 72 67 62 dB Min Input resistance Common mode 5 M Typ Input capacitance Common mode / differential 0.4/0.8 pF Typ Output characteristics Output voltage swing G

46、= +2 1.2/3.8 1.4/3.6 1.5/3.5 V Min Output current (sourcing) RL= 10 120 90 78 mA Min Output current (sinking) RL= 10 65 45 37 mA Min Output impedance f = 1 MHz 0.1 Typ Power supply Specified operating voltage 5 15 15 V Max Maximum quiescent current 20 23 34 mA Max Minimum quiescent current 20 18 13

47、mA Min Power supply rejection (+PSRR) VS+= 5.5 V to 4.5 V, VS-= 0 V 85 70 57 dB Min Power supply rejection (-PSRR) VS+= 5 V, VS-= -0.5 V to 0.5 V 75 65 56 dB Min Power down characteristics (device type 02 only) Power down voltage level 2/ REF = 0 V, or VS-Enable REF + 1.8 v Min Power down REF + 1 Max REF = VS+ or floating Enable REF -1 Min Power down REF 1.7 Max Power down quiescent current PD = Ref + 1 V, Ref = 0 V 650 800 1000 A Max PD = Ref -1.7 V, Ref = VS+650 800 1000 A Max Turn on time delay (t(ON) 50% of final supply current value 4 s Typ T