DLA DSCC-VID-V62 04649 REV B-2010 MICROCIRCUIT DIGITAL FIXED POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct lead finish. Add table I note 1/ reference to all pages of table I. - CFS 05-11-08 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 10-12-08 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PA

2、GE REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 4

3、3218-3990 http:/www.dscc.dla.mil Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY MM DD 04-06-10 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04649 REV B PAGE 1 OF 39 AMSC N/A 5962-V016-1

4、1 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Di

5、gital Signal Processor microcircuit, with an operating temperature range of -40C to +100C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the

6、engineering documentation: V62/04649 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 SM320VC5409-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outline(s) are as

7、 specified herein. Outline letter Number of pins Package style X 144 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD Palladiu

8、mE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage I/O range, (DVDD) . -0.3 V to +4.0 V 4/ Supply voltage core range, (CVDD) . -0.3 V to +2.4 V 4/ Input voltage range, (VI) . -0.3 V to +4.5 V Output voltage range (VO) . -0.3 V to +4.5 V Operating case temperature rang

9、es, (TC): (Extended) . -40C to +100C Storage temperature range, (TSTG) -55C to +150C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to t

10、he device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ Long

11、term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer data for additional information on enhanced plastic packaging. 4/ All voltage values are with respect to VSS. Provided by IHSNot for Resale

12、No reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 3 1.4 Recommended operating conditions. Device supply voltage, I/O (DVDD) +3.0 V to +3.6 V 5/ Device supply voltage, core (CVDD) +1.71 V

13、to +1.98 V 5/ Supply voltage, GND (VSS) . 0 V High level input voltage, I/O (VIH): 6/ +2.2 V to DVDD+ 0.3 V TRST +2.5 V to DVDD+ 0.3 V X2/CLKIN . +1.4 V to CVDD+ 0.3 V All other inputs +2.0 V to DVDD+ 0.3 V Low level input voltage, (VIL): 7/ . -0.3 V to +0.6 V All other inputs -0.3 V to +0.8 V Maxim

14、um high level output current, (IOH) . -300 A Maximum low level output current, (IOL) . +1.5 mA Operating case temperature (TC) . -40C to +100C Junction to air (RJA) +38C/W Junction to case (RJC) . +5C/W 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (

15、Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein an

16、d as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recomm

17、ended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 5/ Manufacturer DSPs do not require specific power sequencing between the core supply and the I?O supply. However, system should be designed to ensure that neither supply is powere

18、d up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System level concerns such as bus contention may require supply sequencing to be implemented. In this cas

19、e, the core supply should be powered up at the same time as or prior to the I/O buffers, and then powered down after the I/O buffers. 6/ RS , INTn , NMI, BIO , BCLKR0, BCLKR1, BCLKR2, BCLKX0, BCLKX1, BCLKX2, HAS , HCS , 1HDS , 2HDS , TCK, CLKMDn, DVDD= 3.3 0.3 V 7/ RS , INTn , NMI, X2/CLKIN, BIO , B

20、CLKR0, BCLKR1, BCLKR2, BCLKX0, BCLKX1, BCLKX2, HAS , HCS , 1HDS , 2HDS , TCK, CLKMDn, DVDD= 3.3 0.3 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 4 3.4

21、 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure

22、 2 3.5.3 Load circuit. The load circuit shall be as specified in figure 3. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 4-24. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE

23、 IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition -40C TC +100C 1.71 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max High level output voltage VOHIOH= Max 2.4 V Low level output voltage VOLIOL= Max

24、 0.4 V Input current for outputs in high impedance D15:0, HD7:0, A15:0 IIZBus holders enabled, DVDD= Max, VI= VSSto DVDD-200 200 A All other inputs DVDD= Max, VO= VSSto DVDD-5 5 Input current (VI= DVSSto DVDD) X2/CLKIN II(VI= VSSto DVDD) -40 40 A TRST With internal pull down -5 200 HPIENA, HPI16 Wit

25、h internal pull down -5 200 TMS, TCK, TDI, HPI 2/ With internal pull ups, HPIENA = 0 -200 5 All other input only pins -5 5 Supply current, core CPU IDDCCVDD= 1.6 V, fclock= 100 MHz, 3/ TC= 25C 4/ 37 Typ mA Supply current .pins IDDPDVDD= 3.0 V, fclock = 100 MHz , 3/ TC= 25C 5/ 45 Typ mA Supply curren

26、t, standby IDLE2 IDDPLL x 2 mode, 50 MHz input 2 Typ mA IDLE3 Divide by two mode, CLKIN stopped 20 Typ A Input capacitance CI5 Typ pF Output capacitance CO5 Typ pF Input clock frequency fclock10 20 MHz See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

27、thout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC +100C 1.71 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit M

28、in Max DIVIDE BY TWO/DIVIDE BY FOUR CLOCK OPTION (PLL DISABLED) Switching characteristics H = 0.5tc(CO) 6/ Cycle time, CLKOUT tc(CO)See figure 4 and 5 40 6/ ns Delay time, X2/CLKIN high to CLKOUT high/low td(CIH-CO)4 17Fall time, CLKOUT tf(CO)2 TypRise time, CLKOUT tr(CO)TypPulse duration , CLKOUT l

29、ow tW(COL)H-2 H Pulse duration , CLKOUT high tW(COH)H-2Timing requirements Cycle time, X2/CLKIN tc(CI)See figure 5 20 6/ ns Fall time, X2/CLKIN tf(CI)8 Rise time, X2/CLKIN tr(CI)Pulse duration, X2/CLKIN low tW(CIL)5 Pulse duration, X2/CLKIN high tW(CIH)MULTIPLY BY N CLOCK OPTION (PLL ENABLED) Switch

30、ing characteristics H = 0.5tc(CO) 6/ Cycle time, CLKOUT tc(CO)See figure 4 and 6 10 ns Delay time, X2/CLKIN high/low to CLKOUT high/low td(CI-CO)4 17Fall time, CLKOUT tf(CO)2 TypRise time, CLKOUT tr(CO)TypPulse duration , CLKOUT low tW(COL)H-2 H Pulse duration , CLKOUT high tW(COH)H-2Transitory phas

31、e, PLL lock up time tp30 s Timing requirements 7/ Cycle time, X2/CLKIN Integer PLL multiplier N (N = 1-15) tc(CI)See figure 6 20 8/ 200 ns PLL multiplier N = x.5 20 8/ 100 PLL multiplier N = x.25, x.75 20 8/ 50 Fall time, X2/CLKIN tf(CI)8 Rise time, X2/CLKIN tr(CI)Pulse duration, X2/CLKIN low tW(CIL

32、)5 Pulse duration, X2/CLKIN high tW(CIH)See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 7 TABLE I. Electrical performance charact

33、eristics - Continued. 1/ Test Symbol Test condition -40C TC +100C 1.71 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max MEMORY AND PARALLEL I/O INTERFACE TIMING Switching characteristics for a memory Read ( MSTRB = 0) 9/ Delay time, CLKOUT low to address valid 10/ td(CLKL-A)

34、See figure 7 0 3 ns Delay time, CLKOUT high (transition) to address valid 11/ td(CLKH-A)0 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL)3 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH)Hold time, address valid after CLKOUT low 10/ th(CLKL-A)R0 3 Hold time, address valid after CLKOUT high 11/ th(

35、CLKH-A)RTiming requirements for a memory Read ( MSTRB = 0) H = 0.5 tc(CO) 9/ Access time, read data access from address valid ta(A)MSee figure 7 2H-10 12/ ns Access time, read data access from MSTRB low ta(MSTRBL)2H-10 12/ Setup time, read data before CLKOUT low tsu(D)R8 Hold time, read data after C

36、LKOUT low th(D)R0 Hold time, read data after address invalid th(A-D)RHold time, read data after MSTRB high th(D)MSTRBH1 Switching characteristics for a memory Write ( MSTRB = 0) H = 0.5 tc(CO) 9/ Delay time, CLKOUT high to address valid 13/ td(CLKH-A)See figure 8 0 3 ns Delay time, CLKOUT low to add

37、ress valid 14/ td(CLKL-A)0 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL)3 Delay time, CLKOUT low to data valid td(CLKL-D)W8 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH)0 3 Delay time, CLKOUT high to R/ W low td(CLKH-RWL)4 Delay time, CLKOUT high to R/ W high td(CLKH-RWH)Delay time, R/ W low

38、to MSTRB low td(RWL-MSTRBL)H-2 H+1 Hold time, address valid after CLKOUT high 13/ th(A)W0 3 Hold time, write adapt valid after MSTRB high th(D)MSHH-3 H+6 14/ Pulse duration, MSTRB low tw(SL)MS2H-2Setup time, address valid before MSTRB low tsu(A)W2H-2Setup time, write data valid before MSTRB high tsu

39、(D)MSH2H-6 2H+6 14/ Enable time, data bus driven after R/ W low ten(D-RWL)H-5Disable time, R/ W high to data bus high impedance tdis(RWH-D)0 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OH

40、IO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC +100C 1.71 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max MEMORY AND PARALLEL I/O INTERFACE TIMING CONTINUED Swi

41、tching characteristics for a parallel I/O port Read (IOSTRB =0) 15/ Delay time, CLKOUT low to address valid td(CLKL-A)See figure 9 0 3 ns Delay time, CLKOUT high to IOSTRB low td(CLKH-ISTRBL)0 Delay time, CLKOUT high to IOSTRB high td(CLKH-ISTRBH)3 Hold time, address after CLKOUT low th(A)IORTiming

42、requirements for a parallel I/O port read (IOSTRB = 0) H = 0.5tc(CO) 15/ Access time, read data access from address valid 12/ ta(A)IOSee figure 9 3H-9 ns Access time, read data access from IOSTRB low 12/ ta(ISTRBL)IO2H-8Setup time, read data before CLKOUT high tsu(D)IOR8 Hold time, read data after C

43、LKOUT high th(D)IOR0 Hold time, read data after IOSTRB high th(ISTRBH-D)RSwitching characteristics for a parallel I/O port Write (IOSTRB = 0) H = 0.5tc(CO) 15/ Delay time, CLKOUT low to address valid td(CLKL-A)See figure 10 0 3 ns Delay time, CLKOUT high to IOSTRB low td(CLKH-ISTRBL)0 Delay time, CL

44、KOUT high to write data valid td(CLKH-D)IOWH-5 H+8 Delay time, CLKOUT high to IOSTRB high td(CLKH-ISTRBH)3 Delay time, CLKOUT high to R/ W low td(CLKL-RWL)0 Delay time, CLKOUT high to R/ W high td(CLKL-RWH)3 Hold time, address valid after CLKOUT low th(A)IOWHold time, write data after IOSTRB high th

45、(D)IOWH-3 H+7 Setup time, write data before IOSTRB high tsu(D)IOSTRBHH-7 H+1 Setup time, address valid before IOSTRB low tsu(A)IOSTRBLH-2 H+2 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, O

46、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04649 REV B PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC +100C 1.71 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max READY TIMING FOR EXTERNALLY GENERATED WAIT STATES Tim

47、ing requirements for externally generated wait states H = 0.5tc(CO) 16/ Setup time, READY before CLKOUT low tsu(RDY)See figure 11-12 7 ns Hold time, READY after CLKOUT low th(RDY)0 Valid time, READ after MSTRB low tv(RDY)MSTRB4H-9Hold time, READY after MSTRB low th(RDY)MSTRB4HValid time, READ after

48、IOSTRB low tv(RDY)IOSTRB5H-9 Hold time, READY after IOSTRB low th(RDY)IOSTRB5H Valid time, READ after CLKOUT low tv(MSCL)0 3 Valid time, READ after CLKOUT low tv(MSCH)HOLD AND HOLDA TIMINGS Switching characteristics for memory control signals and HOLDA , H = 0.5tc(CO) Disable time, address, PS , DS , IS high impedance from CLKOUT low tdis(CLKL-A)See figure