DLA DSCC-VID-V62 04620 REV C-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS OCTAL BUFFER DRIVER WITH TTL COMPATIBLE INPUTS AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04620 REV C-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS OCTAL BUFFER DRIVER WITH TTL COMPATIBLE INPUTS AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04620 REV C-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS OCTAL BUFFER DRIVER WITH TTL COMPATIBLE INPUTS AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(11页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type -02. Update case outline dimensions. Update boilerplate to current revision. - CFS 04-11-22 Thomas M. Hess B Add case outline Y. - PHN 06-05-09 Thomas M. Hess C Update boilerplate paragraphs to current requirements. - PHN 12-02-14 Thomas M.
2、Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F.
3、Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, OCTAL BUFFER/DRIVER WITH TTL COMPATIBLE INPUTS AND 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 03-11-14 APPROVED BY Thomas M. Hess SIZE
4、A CODE IDENT. NO. 16236 DWG NO. V62/04620 REV C PAGE 1 OF 11 AMSC N/A 5962-V031-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04620 REV C PAGE 2 1. SCOPE 1.1
5、Scope. This drawing documents the general requirements of a high performance octal buffer/driver with TTL compatible inputs and 3-state outputs microcircuit, with an operating temperature range of -55C to +125C for device type 01, and an operating temperature range of -40C to +85C for device type 02
6、. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04620 - 01 X E Drawing Device type Case outline Lead finis
7、h number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74ACT244-EP Octal buffer/driver with TTL compatible inputs and 3-state outputs 02 SN74ACT244-EP Octal buffer/driver with TTL compatible inputs and 3-state outputs 1.2.2 Case outlines. The cas
8、e outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MS-013 Plastic small-outline Y 20 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designat
9、or Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04620 REV B P
10、AGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO)
11、(VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 58C/W 3/ Storage temperature range (TSTG) . -65C to +150C 4/ 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 4.5 V to 5.5 V Minimum high level input voltage (VIH) 2.0 V Maximum l
12、ow level input voltage (VIL) . 0.8 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH) . -24 mA Maximum low level output current (IOL) . 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature
13、 range (TA): Device type 01 . -55C to +125C Device type 02 . -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface
14、Mount Packages Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. T
15、hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and out
16、put voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of ov
17、erall device life. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/
18、04620 REV B PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit contain
19、er shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction,
20、and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shal
21、l be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without li
22、cense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04620 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ VCCDevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 4.5 V All 4.4 V 5.5 V
23、5.4 IOH= -24 mA, TA= 25C 4.5 V All 3.86 IOH= -24 mA 01 3.7 02 3.76 IOH= -24 mA, TA= 25C 5.5 V All 4.86 IOH= -24 mA 01 4.7 02 4.76 IOH= -75 mA 3/ 5.5 V 02 3.85 Low level output voltage VOLIOL= 50 A 4.5 V All 0.1 V 5.5 V 0.1 IOL= 24 mA, TA= 25C 4.5 V All 0.36 IOL= 24 mA 01 0.5 02 0.44 IOL= 24 mA, TA=
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